******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes and calibrates eQADC module and cyclically converts choosen * channel, displaying it into terminal window along with its time stamp value. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0 - ANA17 * PS1 - ANA18 * PS2 - ANA19 * PS3 - ANA20 * ********************************************************************************

******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW:   XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:       PPC5674FMVYA264 * Terminal:  19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:      264/200/150/60 MHz * ********************************************************************************

******************************************************************************** * File main.c * Owner David Tosenovjan * Version 0.1 * Date May-31-2023 * Classification General Business Information ******************************************************************************** * Detailed Description: * The purpose of this example is show how to keep data in SRAM memory over SW * reset. * INIT_Derivative (file MPC5607B_HWInit.c) is modified to skip ECC RAM * initialization for SW reset source. Linker command file defines my_ram * section, a data being kept over reset are accesses as address pointer to this * location. After initialization SW resets are periodically triggered, * incrementing data on address test_address_3. * * ------------------------------------------------------------------------------ * Test HW: XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: PPC5607BMLUAM03Y * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys: 64/48 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: none * ********************************************************************************

* Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT3 and PIT2 interrupts are implemented. PIT interrupt toggle LED every second. * * * This example also shows, how to implement IVOR exceptions for core 0. * IVOR1 handler with while(1) loop is ready to use. * * * For correct HW vector mode setup, following files was added to the project: * *  - exceptions.s *  - handlers_vle.s *  - HW_vector.c * * * Following files has been modified (all changes are marked by comment): * *  - 56xx_flash.ld *  - Vector.c *  - MPC57xx__Interrupt_Init.c * *  Following file was removed from project (files are still place in project, but *  not compiled and linked) * *  - intc_sw_handlers.S *  - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW:         MPC567XADAT516, MPC567XEVBFXMB * MCU:             PPC5676RDMVY1 3N23A * Fsys:            180 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to J241, *                    User LED 1 connected to J242. *

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_1 error injection *  capability. The fault is generated on DMA transfer to SRAM. *  After fault generation it is propagated to FCCU unit as NCF[59]. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ********************************************************************************

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4a * Configure PIT timer to trigger interrupt and service it. * Example configures start of z7 cores via SW routine. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx MB + MPC5775K-326DS minimodule * Maskset:  0N76P * Target :  internal_FLASH * Fsys:     265 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Sep-07-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/ Example also contains Lauterbach multicore script as you can see below: It will display 3 Power view instances.

******************************************************************************** * Detailed Description: * DRUN mode with max core frequency(200MHz) generated from PPL0 * This example demonstrates ECC error injection to peripheral RAM *  and ECC error reporting to MEMU * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  1N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *           ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Aug-15-2017     b21190(Vlna Peter)  EIM ECC RAM error injection to DMA added *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5604EEVB64 * MCU:             PPC5604EEMLH 0N10D * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position *                  2-3 fit SCI tx and rx connected * ********************************************************************************

******************************************************************************** * Detailed Description: * * eMIOS0 ch0 is set to SAIC mode generating interrupt on falling edge. * The IGF ch16, connected to eMIOSch0, is set to filter low pulses <1.5us * Intergation filter type is used for falling edge with given threshold. * eMIOS interrupt is called if input signal low pulse is longer than 1.5us. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * eMIOS ch0 (PortG P14-16)--> connect external pulse signal * ********************************************************************************

* Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * Test HW: xPC57xx EVB + MPC5746C minimodule * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Sep-29-2020 b21190(Vlna Peter) Added 20kHz frequency modulation *******************************************************************************/

This example content a basic FMPLL initialization and configuration of Mode Entry module and Clock Generation module. By default active is core 2 -> e200z4 Demonstration of PIT triggering an interrupt on timeout. ******************************************************************************** * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0 Apr-02-2019      b21190        (Vlna Peter) Initial Version 1.1 Sep-19-2019     nxa13250    (Vlna Peter) Added PIT + interrupts *******************************************************************************/

This example contains On-line BIST configuration for MPC5746R in GreenHills compiler. For more details refer to application note AN5427 * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015    b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3     May-24-2016    nxa13250(Vlna Peter)Added Online BIST *******************************************************************************/* ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015    b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3     May-24-2016    nxa13250(Vlna Peter)Added Online BIST *******************************************************************************/

Detailed Description: Demo application measures analog voltage from externally connected humidity sensor HIH-5030. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + HIH-5030 MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:   For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

This example shows I2C communication with NXP PCA24S08 memory. The simple MPC5xxx I2C driver is used, see driver code/description on https://community.freescale.com/docs/DOC-330972.   EVB connection: P1.11 - A[10] .. I2C0 SDA P1.12 - A[11] .. I2C0 SCL   ------------------------------------------------------------------------------ Test HW:  TRK-MPC5606B Maskset:  0N13E Target :  RAM, Flash Terminal: 115200, 8N1 Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0.     PC terminal displays this info ...       You can see following I2C bus signals for particular conditions … Writing byte “H” into address 0x28 Read content of the address 0x28   Writing string “Hello world!” into address 0x152     Reading page (16 bytes) from memory address 0x150  

******************************************************************************** * Detailed Description: * This example demonstrate how to configure CGM (clock generation module) * and supply by clock all main peripherals. At maximum available frequency for system * which is 265MHz. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5775K_356DS minimodule, MPC5775K, * Maskset:  0N76P * Target :     internal_FLASH * Fsys:        265 MHz PLL0 * ******************************************************************************** Revision History: 1.0     Apr-15-2015     b21190(Vlna Peter)  Initial Version *******************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW:  MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset:  0N32E * Target :  internal_FLASH * Fsys:     16MHz IRC as system clock ******************************************************************************** Revision History: 1.0     Mar-13-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and cyclically converts PMC * internal channel as specified by macros CHOOSEN_PMC_ADC_CHNL, * CHOOSEN_PMC_ADC_SCALE and CHOOSEN_PMC_ADC_COMMAND to check particular voltage * level, displaying it into terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then what's generate IVOR1 * exception or FCCU_Alarm_Interrupt. Both function calls MEMU handler. * Example also offers useful macros for MEMU module. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, third LED by second core, initializes and display notice via UART * terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, PPC5646C 0M87Y silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************