This example contain Lauterbach programming script for Off-line BIST configuration with 90% coverage. For more details refer to application note AN5427 - Using the Built-in Self-Test (BIST) on the MPC5746R

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for QOM and FPM. * Connect these pins by wire. Output wave is generated on chnl ETPUB0 (QOM0) * and its frequency is measured on the chnl ETPUB1 (FPM0). * TCR counter frequency is 64MHz, output wave configured as 1MHz ( expected * frequency measured by FPM. Window size is 28us (0x400) thus number of * measured pulses is 28 (27 initally). * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and cyclically converts PMC * internal channel as specified by macros CHOOSEN_PMC_ADC_CHNL, * CHOOSEN_PMC_ADC_SCALE and CHOOSEN_PMC_ADC_COMMAND to check particular voltage * level, displaying it into terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

MPC5744P FlexPWM offers possibility to synchronize the FlexPWM modules via external synchronization. Attached is example application how to properly synchronize 2 FlexPWMs modules: FlexPWMs run with motor control clock (MOT_CLK) with 100MHz frequency: PWM period is 20MHz with 50% duty cycle: Below is figure representing External synchronization of 2 PWM (on this frequency I have 2 clocks delay between synchronization) With adjusted FlexPWM0 channel A0 init value by 2 clocks I have reached following results:

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 * Configure PIT timer to trigger interrupt and service it  * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  0N76P * Target :  internal_FLASH * Fsys:     265 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Sep-07-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/

* Detailed Description: * This example demonstrates how to correctly execute ADC self-test for algorithm S and C. * -------------------------------------------------------------------------------------------------------------------- * Test HW:  MPC57xx EVB + MPC5744P minimodule * Maskset:  1N65H * Target :     internal_FLASH * Fsys:        200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * The example performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI_M1 is configured as master and for DSI function to serialize eTPU channels' * outputs. eTPU to DSI routing is done by SIU configuration. * User can see SPI waveform on the scope or logic analyzer. * ------------------------------------------------------------------------------ * Test HW: MPC5746R-252DC, MPC57xx Motherboard * MCU: SPC5746RMMT5 CTQG1740 1N83M HKBGCTB * Fsys: PLL 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: connect following pins to scope or logic analyzer * PA7: DSPI_M1 SOUT (motherboard pin PP[7]) * PA9: DSPI_M1 SCLK (motherboard pin PP[9]) * PA13: DSPI_M1 CS0 (motherboard pin PP[13]) ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts and initializes software watchdog with window mode * allowed. Window mode is set for 2.5 ms. PIT timer is set to service SWT each * 8 ms, which is inside the window. * * * ------------------------------------------------------------------------------ * Test HW:         XPC560B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5604BE MLL 1M27V * Fsys:            64 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:   * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI1 module is configured as a master, DSPI2 module is configured as a slave. * First, response of slave is initialized by writing to PUSHR register of DSPI2. * Second, we write PUSHR register of DSPI1 to send data from master. * Once data are received on both master and slave, data are read from POPR. * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176DC, MPC57xx Motherboard * MCU:             PPC5746R 1N83M * Fsys:            PLL 200MHz * Debugger:        Lauterbach Trace32 * IDE:             S32DS for Power 2017.R1 * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * Connect PA13 (P8.14) to PS11 (P27.12) * Connect PA10 (P8.11) to PS10 (P27.11) * Connect PG12 (P14.13) to PS13 (P27.14) * Connect PG13 (P14.14) to PS7 (P27.8) * ********************************************************************************

Detailed Description: * This example shows, how to configure Mode entry module and enable required * peripherals only. RTC module is configured to create interrupt every 50ms. * Microcontroller is in in STOP mode most of the time and it is waken-up using RTC * interrupt. * * ------------------------------------------------------------------------------ * Test HW:         XPC560S 144LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5606S 0M25V * Terminal:         * Fsys:            16MHz IRC * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Default * ********************************************************************************

In order to enable the RappID bootloader. It needs to program the C:\Freescale\RAppIDBL\RBF_Files\MPC5744P.rbf file into the MCU. User can use S32DS to program the rbf file to MCU. After that the Rappid bootloader PC utility can communicate with the MCU.

******************************************************************************** * Detailed Description: * This exapmple demonstrates progressive clock switching from full PLL clock * 256MNHz down to 200MHz. * * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  3N45H * Target :  FLASH * Fsys:     256 MHz PLL * ******************************************************************************** Revision History: 1.0     Aug-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Sep-05-2017     b21190(Vlna Peter)  Added FCCU faults clearing 1.2    May-07-2018    nxa13250(Vlna Peter)  PLL switch from 256->200MHz *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 7 amd Alarm state * interrupt calling after injecting fake fault 7. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB * Maskset:  0N50N * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration 1.2    Jun-16-2017    b21190(Vlna Peter)  FCCU fake fault injection 1.3    Jun-16-2017    b21190(Vlna Peter)  FCCU alarm interrupt example *******************************************************************************/

********************************************************************************  Detailed Description:  This example shows ADC triggering from the eTimer1 module.  The OFLAG signal from the eTimer1 channel 5 is fed into ADC1 converter,  so ADC is set up for injected conversion with end of scan interrupt.  Red LED is dimmed based on converted value  ------------------------------------------------------------------------------  Test HW: DEVKIT-MPC5744P rev.B  Maskset: 1N16P  Target : FLASH  Fsys: 160 MHz PLL  Debugger: S32DS ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * System frequency which is modulated is 40MHz. * ------------------------------------------------------------------------------ * Test HW:   MPC57xx EVB + MPC5748G minimodule * Maskset:   1N81M * Target :     SRAM * Fsys:        40 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Jun-30-2017    b21190(Vlna Peter)  Added 20kHz frequency modulation *******************************************************************************/ Measure modulated system Frequency at PG[7] - SYSCLK0 pin.

Hi,    Please update your Cyclone Flash Programming Algorithms for MPC57xx through the link.      http://www.pemicro.com/support/flash_list_menu.cfm     Older code algorithms includes area of HSM. If there are ECC errors in these blocks, the device may stuck in reset. During reset, the SSCM module searches for valid boot header. If it reads corrupted data from HSM blocks, it will not exit the reset.     Newer should be with “NO_BASE_ADDRESS=00F90000/”   https://community.nxp.com/thread/444748   Failed sample waves on PORST vs RESET are as below.    Algorithms in S32DS_Power_v2_1 and S32DS_Power_v2017_R1 are good.     Regards Oliver

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes and display notice via UART terminal. It calculates temperature * using TSENS and printes it to the terminal window. * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module for differnential single scan mode (with choosen GAIN * factor), converts specified command queue and displays results into terminal * window when EOQ is reached. * Differential analog input DAN0+:DAN0- needs to be connect externally between * pins ANA_0 and ANA_1 to see some valid numbers. * EVB potentiomenters can be used for the purpose. * As differential mode has been used, eQADC does not required to be calibrated.             * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) DAN0+ *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) DAN0- * *                    Buttons            --> ADC triggers *                    USER_DEV_1D(J4-2)  --> TPU_A0 (J22-1)                  ********************************************************************************

* Owner:            b21190(Vlna Peter) * Version:          1.6 * Date:               Nov-11-2015 * Classification: General Business Information * Brief:               Example contains startup with PLL0 200MHz as system clock *                        ADC self-test demonstration                       ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015          b21190(Vlna Peter)  Initial Version 1.1        Nov-11-2015        b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2        Dec-02-2015        b21190(Vlna Peter)  Added Flash controller init 1.3        Dec-02-2015        b21190(Vlna Peter)  Fixed system clock init 1.4        Feb-07-2017        b21190(Vlna Peter)  SWT0 and SWT1 disabled in startup 1.5       May-31-2017        b21190(Vlna Peter)  Fixed comments in AC6 (CLKOUT) 1.6        Jul-10-2018        nxa13250(Vlna Peter) Added ADC self-tests *******************************************************************************/