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******************************************************************************** * Detailed Description: * Initializes eQADC module and cyclically converts internal channel 145 (PMC * band gap). It also configures eTPUC and its timebases (TCR1) to feed STAC bus * (SRV1). This timebase is used for timestamp of the ADC conversion result. * Both values (result and timestamp) are displayed in the terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU: PPC5676RDMVY1 3N23A * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 180MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: default ********************************************************************************

******************************************************************************** Detailed Description: Example created as new Application project, see readme.txt for steps to do. The purpose of this demo application is to show you the usage of the FlexCAN module using the S32 SDK API and FreeRTOS. In the first part, the application will setup the board clocks and pins. Then it will configure the FlexCAN module features such as Bitrate and Message buffers It will then create two FreeRTOS tasks, one for receiving frames and one for sending frames. The two user buttons are used to send std message ID=0x1h with 1byte payload as 1 or 0. Based on received std message with ID=0x2h to LEDs are toggled upon data0 byte. Use external 12V to power a board. Connect board with PCAN-USB to display send message and be able to receive some on DEVKIT ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G rev.D1 Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL Debugger: S32DS ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes and calibrates eQADC module and cyclically converts choosen * channel, displaying it into terminal window along with its time stamp value. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0 - ANA17 * PS1 - ANA18 * PS2 - ANA19 * PS3 - ANA20 * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes and calibrates both eQADC modules and cyclically converts choosen * channels, displaying it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0-ANA17 PW08-ANB17 * PS1-ANA18 PW09-ANB18 * PS2-ANA19 PW10-ANB19 * PS3-ANA20 PW11-ANB20 * ********************************************************************************

Error Correcting Codes Implemented on MPC5744P Please be aware this is PRELIMINARY document and may be changed without notice. Related code examples can be found here: Example 1 - MPC5744P 1b+2b_RAM_ECC_error_injection GHS714 Example 2 - MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614 Example 3 - MPC5744P 1b+2b_FLASH_ECC_error_by_UTEST_area_read GHS614 Example 4 - MPC5744P EDC_after_ECC_error_by_UTEST_area_read GHS714

******************************************************************************** Detailed Description: This example shows ADC triggering from the eTimer1 module. The OFLAG signal from the eTimer1 channel 5 is fed into ADC1 converter, so ADC is set up for injected conversion with end of scan interrupt. Red LED is dimmed based on converted value ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5744P rev.B Maskset: 1N16P Target : FLASH Fsys: 160 MHz PLL Debugger: S32DS ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal FLASH (user must choose it in the option at the end of main * function). * ECC error is injected by reading of pre-defined patterns in UTEST area at * addresses 0x00400040 and 0x00400060. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in internal DMA TCD RAM (user must choose it in the option at the end of * main function). * EIM (Error Injection Module) is used to simulate a multi-bit or single-bit * ECC error in DMA TCD RAM (Peripheral RAM). * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal RAM (user must choose it in the option at the end of main * function). * ECC fault is generated with using of core register E2EECSR. If error injection * is enabled (E2EECSR0[INVC]=1) and certain mask is set (E2EECSR0[CHKINVT]), * subsequent write to SRAM creates error in SRAM array. * When corrupted data is read the IVOR1 exception handler is called in case of * multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt handler * is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

* Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * Test HW: xPC57xx EVB + MPC5746C minimodule * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Sep-29-2020 b21190(Vlna Peter) Added 20kHz frequency modulation *******************************************************************************/

* Example of eMIOS configuration for shifted PWM mode ******************************************************************************** * Test HW: MPC5746C minimodule + MPC57xx Motherboard * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Jun-06-2017 b21190(Vlna Peter) eMIOS example with shifter PWM *******************************************************************************/

This config tool simplifies PLL setting calculation and clock configuration for MPC5777C device. Version 1.3 added option to select between 264/300 MHz MCU versions. Follow these steps Note: Macros have to be enabled! 1. Enter frequency of used XOSC and desired PLL0 and PLL1 output. - put values into cells B14, Q13 and Q20 of the "Clocks" sheet - check if it is Valid or Invalid - "PLLconfig" sheet shows possible PLLs configurations 2. Configure System and AUX clock selectors and its Dividers - check calculated frequency of System/Peripheral clocks - if Invalid change source clock and Divider value to keep Max freq 3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: jumper J4 on position 1-2 (choosing CS0) * EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Jun-26-2017 David Tosenovjan Initial version 0.2 Oct-13-2017 David Tosenovjan Lower CLKOUT frequency 0.3 Feb-02-2020 David Tosenovjan Corrected External_SRAM_MMU_init Ported to S32 design studio *******************************************************************************/

******************************************************************************** Detailed Description: Example shows configuration of SIUL External interrupts using SDK driver. EIRQ0 (PA3) and EIRQ11 (PE12) are configured for detecting rising edge. Those pins are connected to switches SW1 and SW2 on DEVKIT board. EIRQ1 (PA6) is configured for detecting falling edge. Within its interrupt routines a LEDs are toggled upon edge detecting. See PinSetting component for pins configuration within "Routing" and "Functionals Properties" tabs. To see falling edge on PA6 just connect pin (J2.1) to GND shortly. * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Target: Debug_FLASH * EVB connection: * Compiler: S32DS.POWER.2017.R1 * SDK release: S32_SDK_S32PA_BETA_2.9.0 * Debugger: S32DS, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Jun-13-2019 Petr Stancik Initial version *******************************************************************************/

This example content a basic FMPLL initialization and configuration of Mode Entry module and Clock Generation module. By default active is core 2 -> e200z4 Demonstration of PIT triggering an interrupt on timeout. ******************************************************************************** * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190 (Vlna Peter) Initial Version 1.1 Sep-19-2019 nxa13250 (Vlna Peter) Added PIT + interrupts *******************************************************************************/

Hello If you want to do nothing on MCU, no-operation is used generally. Additional mnemonics are provided for the preferred forms of no-op, like nop, e_nop, se_nop. (Where the semantics are similar but the binary encoding differ, the standard mnemonic is typically preceded with an e_ to denote a VLE instruction. To distinguish between similar instructions available in both 16- and 32-bit forms under VLE and standard instructions, VLE instructions encoded with 16 bits have an se_ prefix.) When you compile these code within IDE, you can get the results as below. The code could run correctly except __asm__ ("nop"). Some MPC5xxx will stop at __asm__ ("nop"). "nop" gives Book E NOP instruction which isn't valid on VLE only cores. "e_nop" gives 32bit VLE instruction. "se_nop" gives 16bit VLE instruction. Based on the summary within AN4802 (thanks for Randy Dee's working), Qorivva MPC57xx e200zx Core Differences, Book E is not supported by MPC57xx. VLE instruction set is supported only. This is the reason that user should use "e_nop" or "se_nop" except "nop" on MPC57xx or S32R2xx. Cheers! Oliver

******************************************************************************** * Detailed Description: * * Purpose of the example is to show how to intentionally generate FCCU fault * causing reset either directly or by FOSU (simulating by non-handled FCCU * fault). Example configures FCCU, then an error is injected with using of * Noncritical Fault Fake register and after re-booting reset cause is evaluated. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************