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******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

This document shows, how to use CRC gen utility in CodeWarrior for MCU IDE. 1) Create new project in CodeWarrior. 2) Create a file calc_crc.crc in the Project/Project_Settings/Linker_File directory. 3) Open project settings, choose C/C++ Build ->Settings and add the following command to Post-build steps: "${MCU_TOOLS_HOME}/bin/crcgen.exe" "${BuildLocation}/${BuildArtifactFileName}" -crc "${ProjDirPath}/Project_Settings/Linker_Files/calc_crc.crc" -srec "${BuildLocation}/${BuildArtifactFileName}.crc.mot" 26 4) Open calc_crc.crc and configure required parameters. Meaning of single lines is described in CodeWarrior reference manual called Targeting_Microcontrollers I used following code (it is only example) 5) Build your project. 6) File MPC5604B-CRCTest.elf.crc.mot was created Now you have s-record, which contains CRC and which could be loaded to microcontroller.

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM to generate independent * PWM signals from Submodule0. The PWMX output is set for 50% duty. * PWMA/PWMB outputs vary its duty cycles. * The DMA module is used to reload VAL2-5 registers. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : RAM, internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * P11.10 - D[9] .. FlexPWM X[0] output * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use SPI module in extended SPI mode * - DSPI3 is configured as a master * - SPI1 is configured as a slave * - Frame size is configured to 32bit * - Two writes are necessary to load one 32bit frame to TX FIFO * - For more details about the timing settings see application note AN4830 * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * * Mode transition to LPU_STOP is executed. CAN_0 is configured to wake up from * LPU_STOP to LPU_RUN using message with standard IDE = 0 as a wake up * preselected matching criteria. After wake up from LPU_STOP, user * LED1 is blinking. * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW: MPC5748G-324DS, MPC574xG Motherboard * MCU: PPC5748GMMN6A 1N81M * Fsys: PLL0 160MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: Default * * * ********************************************************************************

******************************************************************************** * Detailed Description: * Example demostrates MCU behaviour when single bit RAM ECC error occurs by * intentional ECC error injection. * * ------------------------------------------------------------------------------ * Test HW: xPC564xLKIT, PPC5643L Cut3 silicon * Target : internal_FLASH * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Terminal: 19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW: MPC5688EVB * MCU: SPC5668GMMG 0N61C * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 116 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: User LED 4 connected to pin P28-10 * *

* Owner: b21190(Vlna Peter) * Version: 1.0 * Date: May-09-2018 * Classification: General Business Information * Brief: BIST demonstration * ******************************************************************************** * Test HW: MPC57xx * Maskset: 3N23A * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Oct-22-2014 b21190(Vlna Peter) Initial Version 1.1 Mar-19-2015 b21190(Vlna Peter) Added ADC_0 driver 1.2 Mar-19-2015 b21190(Vlna Peter) Added STCU self-test for core1 *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 15. * ------------------------------------------------------------------------------ * Test HW: MPC57xx EVB + MPC5777M minimodule * Maskset: 0N50N * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Nov-04-2014 b21190(Vlna Peter) Initial Version 1.1 Feb-04-2016 b21190(Vlna Peter) Fixed Clock configuration 1.2 Feb-06-2017 b21190(Vlna Peter) FCCU fake fault injection *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW: S32R274RRUEVB, MPC57xx Motherboard * MCU: S32R274KAMMM 1N58R * Fsys: PLL0 240MHz * Z4 Core 120MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: * * It is necessary to remove both J35 jumpers. * * * Connect J35.2 to PA14 (CAN_1 TX) * Connect J35.4 to PA15 (CAN_1 RX) * * CAN0 is connected internally to J37 (this pin is placed on daughter card) * * Connect CAN P5.2 to J37.2 (CAN_1 and CAN_0 CANL) * Connect CAN P5.1 to J37.1 (CAN_1 and CAN_0 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Example shows how to use original eTPU sets available over eTPU Function * Selector ( https://www.nxp.com/webapp/etpu/ ) and integrate them into * S32 Design Studio Integrated Development Platform. Example is based on * Software Development Kit (SDK) startup, in the main function adds necessary * configuration to get eTPU run. * eTPU application itself is simple PWM configured with eTPU Graphical * Configuration Tool. Target CPU is 'Generic CPU with eTPU2', eTPU clock 100MHz. * User can shows PWM waves over pins PH[10] and PH[11]. * * Tip: AN4687 may be used as reference with note the different compiler is used. * References: http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf * https://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT * ------------------------------------------------------------------------------ * Test HW: MPC5746R-176DC Rev.A2 + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5743RMLU5 QCO1640 1N83M FEAEQL * Target: Debug_FLASH * EVB connection: ETPU0_A (Port PH[10]) --> scope * ETPU1_A (Port PH[11]) --> scope * Compiler: S32DS.Power.2017.R1 * SDK release: S32_SDK_S32PA_EAR_1.8.0 * Configurator: eTPU Graphical Configuration Tool 1.4.0.4 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash * and Flash over Flash. The remapping is visible only in mirrored flash address * space. Normal address space is not affected. To see effect of the remapping, * read the comments and watch following addresses in debugger before and after * executing Overlay() function: * * Flash over Flash test case: * 0x0104_0000 * 0x0108_0000 * 0x0904_0000 * 0x0908_0000 * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Fsys: PLL0 160MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode) * EVB connection: NA * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrate how to configure CGM (clock generation module) * and supply by clock all main peripherals. At maximum available frequency for system * which is 265MHz. * ------------------------------------------------------------------------------ * Test HW: MPC57xx Motherboard + MPC5775K_356DS minimodule, MPC5775K, * Maskset: 0N76P * Target : internal_FLASH * Fsys: 265 MHz PLL0 * ******************************************************************************** Revision History: 1.0 Apr-15-2015 b21190(Vlna Peter) Initial Version *******************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW: MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset: 0N32E * Target : internal_FLASH * Fsys: 16MHz IRC as system clock ******************************************************************************** Revision History: 1.0 Mar-13-2017 b21190(Vlna Peter) Initial Version *******************************************************************************/