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******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_0 error injection *  capability on XBAR_0. The fault is generated on Core access to SRAM. *  After fault generation it is propagated to FCCU unit as NCF[38]. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     16MHz IRC * ********************************************************************************
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This is the first lab for the 2D-ACE (DCU) tutorial
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Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI Simple weather station demo using 2 external sensors and  external real time clock/calendar   For detailed description SEE ATTACHED document. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:  1) Temperature sensor LM75B:                        J51.40 - F[6] -> LM75B SDA                        J51.43 - F[7] -> LM75B SCL                        J52.1  - 3.3V -> LM75B Vcc                        J50.1  - GND  -> LM75B Gnd                   2) Humidity sensor HIH-5030:                        J52.1  - 3.3V -> HIH-5030 Ve+                        J50.1  - GND  -> HIH-5030 Ve-                        J50.1  - ANS0 -> HIH-5030 Out                   3) External Real Time Clock:                        J51.40 - F[6] -> PCA8565 SDA                        J51.43 - F[7] -> PCA8565 SCL                        J52.1  - 3.3V -> PCA8565 Vcc                        J50.1  - GND  -> PCA8565 Gnd                                        *******************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use some of ETimer modes. Channel 0 is set to * Fixed-Frequency PWM Mode and generates PWM signal with approximate frequency * 507Hz. This signal is routed to the UserLED1. * * Channel 1 is set to Count mode and generates 0,25 second interrupt. * In the interrupt service routine, duty cycle is increased from 0% to 100% * with step 6.25%. This shows for example, how can be controlled the brightness * of the LED. * * Channel 2 is set to Variable-Frequency PWM Mode and generates PWM signal with * frequency 10KHz. This signal is routed to the UserLED2. * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Terminal: * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  UserLED1 connected to P19.0 *                     UserLED2 connected to P19.2 * * ********************************************************************************
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The purpose of the example is to present advantage of streaming mode feature.   Example initializes eQADC module, converts specified command queue and displays results into terminal window. Used analog inputs ANB_0 and ANB_1 requires external connection to converted voltage (potentiometer) to see some valid numbers. Following channels are being converted: CH0 = signal ANB_0 (connect pot USER_DEV_RV2(J4-7) --> ANB_0 (J19-3)) CH1= signal ANB_1 (connect pot USER_DEV_RV3(J4-8) --> ANB_1 (J19-4)) CH2 = may be left open (example configures the pin to be pulled-up) CH3 = may be left open (example configures the pin to be pulled-down) Result are being filled to 2 result queues to see loop switching in the terminal window when advance trigger occurs (results are displayed in two columns, 1st column is related to Rqueue0, 2nd to Rqueue1). Advance trigger occurs when EVB's USER switch 1 is being pressed (considering USER_DEV_1D(J4-2) --> TPU_A0 (J22-1)). Repeat trigger is initiated automatically by PIT3 timer in 1 sec intervals. eQADC command filled by eDMA, results drained by interrupt service routines.   For detailed description SEE ATTACHED document.
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******************************************************************************** * Detailed Description: * ECSM Error Generation Register EEGR is used to generate a non-correctable ECC * error in RAM. The bad data is accessed then, so the IVOR1 exception is * generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can select particular ME/EE setup by * comment/uncomment of particular function calls. * * ------------------------------------------------------------------------------ * Test HW:        XPC563MKIT * MCU:            PPC5633MMLQ80 * Fsys:           80/60/40/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************
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The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now.   ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW:    X - PC5748G - MB (rev C) * MCU:        PPC5748GMMN6A * Maskset:    1N81M * Fsys:       160 MHz * Debugger:   Lauterbach Trace32 *              * Target:     Internal_FLASH * ********************************************************************************
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This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device.                  Follow these steps                  Note: Macros have to be enabled!                  1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.                 - put values into cells B11, Q10 and Q17 of the "Clocks" sheet                 - check if it is Valid or Invalid                 - "PLLconfig" sheet shows possible PLLs configurations                  2. Configure System and AUX clock selectors and its Dividers                 - check calculated frequency of System/Peripheral clocks                 - if Invalid change source clock and Divider value to keep Max freq                    3. Copy generated code by pressing "Copy Code" button
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In order to enable the RappID bootloader. It needs to program the C:\Freescale\RAppIDBL\RBF_Files\MPC5744P.rbf file into the MCU. User can use S32DS to program the rbf file to MCU. After that the Rappid bootloader PC utility can communicate with the MCU.
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******************************************************************************** * Detailed Description: * * * This example shows synchronization between FlexPWM, CTU and ADC modules. * The FlexPWM Submodule 0 is initialized to generate PWM signal, and rising edge * of PWM B0 signal is used to generate trigger signal for CTU module. The CTU module * sends two commands to ADCs. Single conversion mode is used, so ADC0 ch0 and ch1 * are sampled. The conversion result is used to modify PWM B0 rising egde position * and change delay between external trigger and ADC sequence triggering. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output   * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * connect Trimmer J53.1 to P9.1 to change position of PWM B0 rising edge * connect Trimmer J53.1 to P9.2 to change CTU trigger delay from PWM B0 rising edge * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of PWM signals * ********************************************************************************
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******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   Switches on Motherboard: *   P6.1 to P8.1  ... SW1 to PA0 *   P6.2 to P8.2  ... SW2 to PA1 *   P6.3 to P8.3  ... SW3 to PA2 *   P6.4 to P8.4  ... SW4 to PA3 * *   Unconnect LINFlexD_0 from UART transceiver *   J14 SCI_RX open *   J13 SCI_TX open * *   As only single LIN transceiver is available LINFlex modules are connected *   together before this transceiver in the way TX pins together and RX pins together. *   TX pins must be configured as open drain and use a pullup resistor. * *   P11.15 to P12.8    TX pins *   P11.16 to P12.7    RX pins * *   Connect LINFlexD_1 to LIN transceiver on Motherboard *   J17 - LIN_TX ON *   J16 - LIN_RX ON *   J15 - LIN_EN ON *   P3 1-2 ON ... VSUP to 12V ** *   See LIN signal on P3.3 or J4.4. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: None ******************************************************************************** Revision History: 1.0     Feb-22-2016     PetrS          Initial Version of LIN example *******************************************************************************/ Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip
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******************************************************************************** * Detailed Description: * * Configures the FlexCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. * Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. * * In this config, CAN_0 transmits a message. CAN_1 receives the message. * * EVB connection: * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * NOTE! Termination resistor (120Ohm) have to be placed on transceivers output * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************
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******************************************************************************** * Detailed Description: * Read attached document "How to use Register Protection on MPC5748G.pdf" * for detailed explanation. * This example shows how to lock and unlock register MC_ME.RUN_MC[3].R. * One option is to write directly to memory via pointers, second option is * to use macros from header file reg_prot.h. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************
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******************************************************************************** * Detailed Description: * This example demonstrates basic functionality of SARADC (10-bit ADC0 and 12-bit ADC1) in one-shot conversion mode. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Mar-10-2016    b21190(Vlna Peter)  Added ADC driver *******************************************************************************/
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******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is enabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Install jumpers J37 1-2 and J38 1-2 * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * ********************************************************************************
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******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message  Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 16 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. MB10 is moreover used to receive a message with given standard ID. MB11 is used to transmit a message upon button press. The callback function is installed as well and is it called each time message is received in MB10, RXFIFO or message is transmitted. NOTE! Termination resistor (120Ohm) have to be placed on transceivers output             12V power supply must be connected. ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL ********************************************************************************
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******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4)                * ********************************************************************************
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******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 0 and * displays results into terminal window by interrupt service routine. Analog * input AN[0] requires external connection to converted voltage (potentiometer). * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: USER_DEV pin RV2(i.e. pin8) -> pin B7 on I/O header ring *                 (potentiometer RV2 to analog input AN[0])   * ********************************************************************************
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Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference
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******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:        This example demonstrate SWT functionality *                 On SWT timeout it sent signal to FCCU where is long *                 functional reset reaction on SWT timeout configured *                 FCCU then sent signal to RGM module which triggers long *                 functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1     Mar-24-2015    b21190(Vlna Peter)  Added SWT long reset *******************************************************************************/
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