Ⅰ、Introduction The MCUXpresso Secure Provisioning Tool (SEC) tool is a GUI-based application provided to simplify generation and provisioning of bootable executables on NXP MCU platforms. The latest version of SEC v8 adds FCB configuration function to help users program image to external flash. The MCX N94x family is a typical product series of MCX. A controller with a flexible serial peripheral interface (FlexSPI) that supports external memory. The external flash has a large storage capacity, high flexibility. It is relatively independent of the replacement or upgrade of the main chip, and has high reliability and lifecycle. This article focuses on how to use SEC tools to configure and program MCXN947 external flash quickly and easily. Ⅱ、Configuration steps This article uses the FRDM-MCXN947 board as an example to configure FCB and download an external flash image. Hardware requirements: FRDM-MCXN947 board、Type-C USB cable Software requirements: MCUXpresso Secure Provisioning Tool | NXP Semiconductors Step1. Create new workspace  After opening the software, click File->New Workspace, select "MCX N94x/N54x" -> MCXN947 -> Click "create". Refer to the following figure: Step2. Connection with Target Processor Enter ISP mode：Press and hold SW3(ISP key) => Press and release SW1 (RESET key) => Release SW3 Go to your workspace and click “Target”->Connection, the Connection with Target Processor window is displayed. Here, we make Connection through UART and select port and baud rate. Refer to the following figure: We can click "Test connection" to check whether the connection is successful. If the connection is successful, the result will display "OK". Refer to the following figure: Step3. Boot memory configuration Next we need to configure FCB. Click on "Target"-> Boot Memory… ,The Boot memory configuration window is displayed. First we need to select the Boot memory type, this part allows selection of the boot memory type, and optionally instance. The selection contains all memory types but unsupported types are disabled. FlexSPI NOR flash can be configured in two ways: By using the flashloader/ROM based simple configuration in the Boot Memory Configuration dialog or By using the complete FCB (FCB binary), which can be prepared from the boot device configuration as well, or via MCUXpresso IDE by adding the FCB component into Peripheral Drivers in Peripherals tools, where the full configuration can be specified. Here we use a simple configuration, click "FlexSPI NOR-simplified", on this Predefined template, select W25Q64JW and click apply. Then, corresponding parameters on W25Q64JW will be automatically created on Boot memory configuration parameters. Normally, keep the default value. Refer to the following figure: We use "Test the configuration" to check whether the configuration is correct. After clicking "Test", the script will pop up to run automatically, and "SUCCESS" will be displayed after running. Refer to the following figure: Then click "convert to FCB" and the "convert to FCB" dialog box will pop up. Keep the default position of "FCB file path". Select "Apply the converted FCB as boot device configuration" and click "convert". The script automatically runs and generates "converted_fcb.bin". The FlexSPI NOR-complete FCB window is displayed. Refer to the following figure: The generated converted_fcb.bin file is automatically loaded to FCB file for runtime and FCB File for write. Click "Test" and "SUCCESS" will be displayed. Click "OK" to close the window. Refer to the following figure: Step4. Build image After completing the above operations, we need to load the .s19 or .hex file generated by MCUXpresso IDE into the Source executable image. Note: The start address of the external flash of the project needs to be changed to 0x80001000. This section does not explain how to change the start address. For details, see “How to config booting from external flash”. After the file is loaded, the start address is automatically identified. If the start address is not 0x80001000, you cannot "built image". Then click on "built image". Refer to the following figure: After completing the built image, "SUCCECC: built image" will be displayed. Click "close". Refer to the following figure: Step5. Write image We can see that the required .bin file has been generated automatically in "write image", or we can import the corresponding .bin file we wrote by "import". The Image path file will be automatically loaded. Click "write image" to run the script automatically. After the file is successfully written, "SUCCESS: write image" is displayed. Refer to the following figure: Finally, by pressing the RESET key on the board to exit ISP mode, we completed the configuration and downloaded the external flash image. Ⅲ、Summarize We use SEC Tool to configure FCB and download external flash images via GUI. This is just a simple method, and users can choose different ways according to their requirements.

  This guide helps you to: Get familiar with NPU inside the MCX Know eIQ ML examples included in SDK. Summarize related application notes and demo projects on GitHub Prerequisites: Windows 10 development PC. FRDM-MCXN947 board NXP’s  MCUXpresso IDE is installed on the development PC Generate and download FRDM-MCXN947 SDK package from the web-based MCUXpresso SDK builder. Introduction to NPU The MCXN94x and MCXN54x are based on dual high-performance Arm® Cortex®-M33 cores running at up to 150 MHz, it has 2MB of on-chip Flash with optional full ECC RAM and an integrated proprietary NPU. The integrated NPU delivers up to 40x faster machine learning (ML) throughput compared to a CPU core, enabling it to spend less time awake and reducing overall power consumption. The architecture provides power and performance-optimized NPUs integrated with NXP's very wide portfolio of microcontrollers and applications processors. The eIQ Neutron NPUs offer support for a wide variety of neural network types such as CNN, RNN, TCN, and Transformer networks and more. ML application development with the eIQ Neutron NPU is fully supported by the eIQ machine learning software development environment. The NPU used in MCXN94 is Neutron N1-16, its block diagram is shown in the below figure. The eIQ Neutron N1-16 NPU found inside the MCXN94 has 4 compute pipes and each compute pipe contains 4 INT8 MAC (Multiply Accumulate) blocks for a total of 16 MAC blocks. This means that MCXN94 could execute 4.8G(150MHz * 4 * 4 * 2) INT8 operations per second. The MCUXpresso Software Development Kit (MCUXpresso SDK) provides a comprehensive software package with a pre-integrated TensorFlow Lite for Microcontrollers (TFLM). The Neutron library is integrated into TFLM as well. The following table shows the operators which are supported by the NPU. Operator Operator input type MCXN947/MCXN548 NPU ADD Float No Uint8(PTQ) No Int8(PCQ) Yes AVERAGE_POOL_2D Float No Uint8(PTQ) No Int8(PCQ) Yes CONV_2D Float No Uint8(PTQ) No Int8(PCQ) Yes DEPTHWISE_CONV_2D Float No Uint8(PTQ) No Int8(PCQ) Yes FULLY_CONNECTED Float No Uint8(PTQ) No Int8(PCQ) Yes UNIDIRECTIONAL_SEQUENCE_ LSTM Float No Uint8(PTQ) No Int8(PCQ) No LOGISTIC (Sigmoid) Float No Uint8(PTQ) No Int8(PCQ) Yes MAX_POOL_2D Float No Uint8(PTQ) No Int8(PCQ) Yes MUL Float No Uint8(PTQ) No Int8(PCQ) No SOFTMAX Float No Uint8(PTQ) No Int8(PCQ) No SVDF Float No Uint8(PTQ) No Int8(PCQ) No Note: PTQ — Per-tensor quantized (asymmetric 8-bit quantization). PCQ — Per-channel quantized (symmetric 8-bit quantization). For more information please refer to eIQ TensorFlow Lite User's Guide.pdf in middleware/eiq/doc of SDK. eIQ ML examples included in SDK. Download SDK and select FRDM-MCXN947 in MCUxpresso SDK Builder, Remember to select eIQ middleware. Then open MCUXpresso, it’s convenient to install the SDK by dragging and dropping the file into the SDK installation window of the MCUXpresso IDE. Import SDK examples into the workspace: There are 7 ML examples included in SDK: Here are the descriptions of the eIQ examples: eIQ example Description Hardware requirements tflm_cifar10 CIFAR10 example based on TensorFlow Lite Micro, recognizes a static image FRDM-MCXN947 USB type-c cable tflm_kws Keyword spotting example based on TensorFlow Lite Micro recognizes a static WAV audio FRDM-MCXN947 USB type-c cable tflm_label_image Label 1000 classes of images based on TensorFlow Lite Micro FRDM-MCXN947 USB type-c cable mpp_camera_mobilenet_view_tflm Label camera images based on TensorFlow Lite Micro FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable mpp_camera_ultraface_view_tflm Face detection using the camera as the source, based on TensorFlow Lite Micro FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable mpp_camera_view A simple camera preview pipeline. FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable tflm_modelrunner TFLite Model Benchmark example for Microcontrollers. FRDM-MCXN947 RJ45 Network cable For additional information and guidance, kindly refer to the README file located in the doc folder that accompanies each example. Summary of related application notes There are two application notes available that provide information on advanced usage of NPU. How to Integrate Customer ML Model to NPU on MCXN94x Face Detection demo with NPU accelerated on MCXN947. Please find the notes on the NXP website Summary of demo projects on GitHub There are five demos on nxp-appcodehub from GitHub: Multiple Face detection on FRDM-MCXN947 Multiple person detection on FRDM-MCXN947 Label CIFAR10 images on FRDM-MCXN947 Fashion-MNIST recognition on FRDM-MCXN947 NPU vs TensorFLM benchmark on MCX  

Abstract   This Knowledge Base text is intended to be an introduction for the MCX A14x/15x Architecture. Therefore, the content that is presented is described in a simplified way.   Contents 1. Introduction  2. Bus and Memory Architecture  3. MCX N vs MCX A series  4. MCXA SoC Power Domain Configuration 5. Clock Tree  6. Life Cycle and ROP State  7. Closing remarks    1.    Introduction   The MCX is the new MCU for NXP generic-purposes microcontrollers. Its portfolio offers a comprehensive selection of Arm® Cortex®-M based MCUs offering expanded scalability with breakthrough product capabilities simplified system design, and a developer-focused experience thought the widely adopted MCUXpresso suite of software and tools. Particularly, the MCXA series MCUs expands the MCX Arm® Cortex®-M33 product offerings with multiple high-speed connectivity, operating up to 96 MHz, serial peripherals, timers, analog and low power consumption. This device has following target applications: Consumer and industrial IoT Industrial Communications Smart Metering Automation and Control Sensors The following figure shows a top-level organization of the modules within the chip organized by functional category. Figure 1. Features block diagram   2.    Bus and Memory Architecture   The memory system of the device includes SRAM, ROM, internal flash, and external memory. The following figure shows the Bus matrix block diagram of this chip. Where there are three bus initiators (CM33, DMA and USB FS) which to access to different slave ports thought a Multilayer AHB bus matrix. ROM, Flash and RAMX0/1 share the same slave port. RAMA0/1 share a second slave port. And the third slave port is used to access to the peripherals.   Figure 2. Bus matrix block diagram   The Bus matrix block diagram has de following features: CM33 Max speed is 96MHz Does not include MPU, FPU, DSP and Trustzone Cache 4KB LPCAC on CM33 code bus 8-way, 2-set-associative design based on 256-byte superpages. The access to flash can be cached. Write through Flash Up to 128KB flash. Line buffer and prefetch buffer IFR0 sector0 is CMPA region Memory Block Checker (MBC) is used to control the access permission Swap RAM SRAM is divided into Code TCM and System TCM: CTCM: Mapped to CM33 code bus space RAM X0: 8 KB 32-bit RAM RAM X1: 4 KB 32-bit RAM Can only be used as code RAM when LPCAC is disabled. STCM: Mapped to CM33 system bus space: RAM A0: 8 KB 32+7-bit ECC RAM RAM A1: 16 KB 32bit RAM Execute permission is configurable Remap When remap is enabled, the access to RAM X0, will be remapped to the end of system RAM   3.    MCX N vs MCX A series   The MCX N series have feature-rich on-chip accelerators and peripheral sets. Aimed at applications that need higher performance and fast features. The MCX A series have several device options for a wide range of applications. Provides coverage for all applications requiring microcontrollers in entry-level target products. The following table summarizes the main features of the MCX A and the MCX N series to compare their differences. Table 1. Feature Comparison between MCX N and MCX A series Description MCXN94x MCXA14x/15x Comments System 2x DMA3, CRC, 2x WWDT, SPC, SCG, EIM, ERM, INTM, EWM, SYSCON, WUU, CMC, VBAT 1x DMA3, CRC, WWDT, SPC, SCG, CMC, VBAT, EIM, ERM, SYSCON, WUU - MRCC in MCXA SYSCON is used to control peripherals’ clock select, clock divider and clock gating. - SPC and SCG programming model is forward compatible with MCXN. Security S50, PKC, PUF, TRNG, SM3, 2x GDET, Tamper, eFuse, ITRC, 2x CDOG, LVD/HVD, ROP (Read out protection), 1x CDOG, GLIKEY   Clocking 2x PLL, FRO144M, FRO12M, OSC48M, OSC32K, FRO16K FRO192, FRO12M, OSC48M, FRO16K - OSC48M min. frequency is reduced to 8MHz. Communications USB FS, 10x LP_FLEXCOMM,  2x FlexCAN, 2x SAI, 2x I3C, FlexIO, 2x EMVSIM USB FS, 2x LPSPI, 3x LPUART, LPI2C, I3C - LPSPI/LPUART/LPI2C are compatible with LP_FLEXCOMM. FIFO depth in MCXA is 4, and MCXN is 8. - I3C is new version in MCXA. It is compatible with MCXN - USB FS doesn’t support USB DCD in MCXA. High Speed Interface USB HS, FlexSPI, SDHC, ENET, eSPI, SPI Filter LPSPI (LP_FlexCOMM) LPSPI   Timers 2x FlexPWM, 2x QDC, 5x Ctimer, SCT, uTimer, OS Timer, RTC, 2x LPTMR, MRT 1x FlexPWM, 1x QDC, 3x Ctimer, SCT, uTimer, OS Timer, Wakeup Timer,  LPTMR - FlexPWM and Ctimer support up to 192MHz clock - 3 Sub Modules in FlexPWM of MCXA - QDC is a new design, but compatible with MCXN Analog 2x 16bit ADC, 3x DAC, 3x CMP, 3x OPAMP, VREF, TSI 1x 12bit ADC, 2x CMP - The ADC MCXA is single ended ADC, with single sample/hold circuit. Supports up to 4Msps in 12bit mode. Regulators DCDC, SYS_LDO, CORE_LDO, VBAT, SRAM_LDO OD/SD/MD RUN Mode CORE_LDO, SRAM_RET_LDO   Power Mode RUN Mode: OD/SD/MD LP Mode: Sleep/DS/PD/DPD/VBAT RUN Mode: SD/MD LP Mode: Sleep/DS/PD/DPD   IO 6 rails, 124 GPIO, 100M/50M/25M IO 2 rails, ~52 GPIO, 50M/25M IO High Drive IO, 5V Tolerant IO   NEW MODIFIED       New and modified features are highlighted. And as it can be seen, most of the features of the MCX A are compatible with the MCX N.   4.    MCXA SoC Power domain configuration   The following figure introduce in a simplified way the Power Architecture block diagram of the MCX A. Where it can be seen that consist in three power supplies (VDD, VDD_ANA and VDD_USB) to power system and peripherals.   Figure 3. Power Architecture   VDD is the main supply which powers SYSTEM Domain, PMC, LDO_CORE and IO. At the same time CORE_MAIN Domain is supplied by LDO_CORE. VDD_ANA supplies ADC. And VDD_USB supplies USB FS PHY. Power Architecture has the following features: Run Mode SD mode with 1.1V VDD_CORE, 96MHz max. MD mode with 1.0V VDD_CORE, 48MHz max. Low Power Mode Sleep Mode DS Mode PD Mode CORE_MAIN domain and RAM are retained in different voltage DPD Mode. CMC and SPC control the LP mode, which is compatible with MCX N RAM Retention 3 RAM retention groups, which can be retained independently RAM X0 and RAM X1 RAM A0 RAM A1 All RAM can be retained down to DPD mode RAM retention control logic is implemented in SPC Power Sequence VDD and VDD_ANA must be ramp up same time with same level Voltage Monitors POR on VDD LVD and HVD on VDD LVD on VDD_CORE VDD_USB detector The following figure shows the Power Mode Transition block diagram. After POR the chip enters in Reset, when it exits from Reset the chip enters Active Mode. By performing Active Mode, it is able to enter all Low Power Modes. In Sleep and Deep Sleep Modes, it is possible to return directly to Active Mode. Meanwhile, to exit from Deep Power Down Mode, a Reset must be performed. Figure 4. Power Modes Transition   5.    Clock Tree   The following Figure shows a high level of Clock Architecture block diagram. In the left of the block diagram there are the on-chip clock sources, meanwhile in the right there is the distribution of the clock signals that clocking the systems and peripherals of the chip. The SCG controls FRO192M, FRO12M and SOSC clock sources. VBAT implements the 16 kHz internal clock source. And the MRCC provides on-chip modules their own dedicated MRCC bits for clock gating, reset control and configuration options. Figure 5. Clock Architecture The Clock Architecture has the following features: Clock Source FRO192M. Outputs 192/96/48MHz FRO12M. Outputs 12MHz and 1MHz. SOSC. Supports 8~50MHz FRO16K. Output 16.384KHz Clock Management Overall clock architecture is same with MCXN SCG and VBAT control clock generators MRCC in SYSCON controls clock mux and clock divider of the system and peripherals.   6.    Life Cycle and ROP State The following Table summarizes the Life Cycle State model and the Read Out Protection (ROP), which are designed to protect customer code and data from reading from the device internal flash. There are different levels of protection in the system, so that access to the on-chip flash and use of ISP can be restricted. Also, the life cycle state of the device determines the debug access and ISP command availability. Table 2. Life Cycle and ROP Life Cycle State ROP State Debug Port Status Debug Mail Box Command ISP Command NXP_PROVISIONED OEM_OPEN OEM_FIELD_RETURN NXP_FIELD_RETURN ROP0  ROP_STATE = 0xFFFF_FFFF  ROP_STATE_DP = 0xFFFF_FFFF - Disabled by default - Enabled by Bootloader Full command OEM_CLOSED ROP1    ROP_STATE = 0x0000_0003    ROP_STATE_DP = 0x0000_0003 - Disabled by default - Not enabled by Bootloader - Debug configure register is not locked Reduced command ROP2    ROP_STATE = 0x0000_0001    ROP_STATE_DP = 0x0000_0001 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked Reduced command OEM_NO_RETURN ROP3    ROP_STATE = 0x0000_0000    ROP_STATE_DP = 0x0000_0000 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command BRICKED Other value - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command   NXP_BLANK and NXP_FAB are NXP states that are not available for customers. NXP_PROVISIONED, OEM_OPEN, OEM_FIELD_RETURN and NXP_FIELD_RETURN are initial customer development states after leaving NXP manufacturing. OEM_CLOSED is the customer in-field application state, with ROP protection. OEM_NO_RETURN is the customer in-field application state, with ROP protection which prevents use of field return. And finally, BRICKED is the end-of-life state to prevent device use.   7.    Closing remarks   The MCX A series is based on the Arm Cortex-M33 operating at up to 96 MHz. It is scalable and easily migrated between N and A series given that peripherals and memories are very similar. The main on-chip memories are a Non-Volatile Flash memory with ECC and a RAM with ECC and Self-Test. Enhanced peripherals are designed with specific use cases in mind. This gives the applications a lot of focus on what they need. Improved Read Out Protection is built into the hardware designed to protect customer code and data from unauthorized readings. This device provide great flexibility and multiple options for the user to achieve low-power consumption with memory retention. Comprehensive serial communications included in the MCX A allow to interact with various components in customer applications. The analog integration selection within the MCX A also provides real-time response to the outside world, including ADC, CMP and temperature sensor. Utilize MCUXpresso software and tools to optimize, ease and help accelerate your embedded system development with a development suite that includes device configuration tools, drivers and middleware, multiple IDEs and a secure provisioning tool.

Device manufacturers spend months or years developing application software for their end products, which is one of the most valuable assets.   During the software development phase, the engineering teams use development platforms with easy access to critical electronics development components, but this is no longer the case when the projects move to the manufacturing phase. Once the project is ready to go to manufacturing the exposure of the electronics components changes drastically from a development environment. In Most cases the programming connector is not accessible because PCB now resides inside an assembled enclosure or has been removed to reduce PCB cost or very important, for security reasons. On Any case you still need to download manufacture testing FW or final product firmware to the microcontrollers in the system and to help with that NXP MCX microcontrollers have embedded tools called the In-system programming to assist with the FW provisioning. In-System programming (ISP) is a method of erasing and programing the on-chip FLASH or RAM memory using a ROM bootloader firmware without using an external Debug tool. NXP MCX Microcontroller family have ISP support over several serial peripherals like: UART SPI I2C USB High-Speed USB Full-Speed CAN Depending on the MCX microcontroller you are using the ISP supported peripherals will change so it is important to review the “In-system Programming” reference manual chapter on the specific MCX microcontroller that will be used. One important thing to remark is that the ISP firmware resides inside a ROM section on the MCX microcontrollers, meaning that the entire flash of the device can be used for the main application without the need of reserving on-chip FLASH for a firmware provisioning bootloader. The flash bootloader code is executed automatically every time the part is powered on or reset. The bootloader can execute the ISP command handler or pass execution to the user application code depending on several conditions. When the internal flash in empty the MCX microcontroller automatically enters ISP mode. Translating this to the manufacturing, Microcontrollers are ready to get firmware using ISP after the PCB assembly process. In-circuit programming features can be tested using any FRDM or EVK boards available for MCX family. You can find instructions of how to use the ISP mode alongside many other MCX examples, demos and tools directly on NXP Application Code Hub   Here are some Application Code Hub for ISP on MCX FRDM boards: How to use In-System Programming (ISP) on FRDM-MCXN947 How to use In-System Programming (ISP) on FRDM-MCXA153   Security is at the core of NXP. Not only do we want each element of our devices or software to be safe and secure, but it is just as critical that we enable the manufacturing of each customer's product to be secure. Manufacturing processes should be worry-free and hassle-free with the backing of highly secure technology, even if the manufacturing site itself cannot provide strong assurances of security. NXP is offers a variety of features that enable OEMs to protect their IP and revenue. Utilizing our MCUXpresso Secure Provisioning tool (SEC) and Secure Provisioning SDK (SPSDK)   MCXpresso Secure Provisioning tool (SEC) The MCUXpresso Secure Provisioning tool (SEC) is a GUI-based application that provides firmware provisioning operations such as setting up e-fuses/OTP, building secure boot image, flash programming, keys generation, trust provisioning, etc.   NXP SEC tool features: Easy-to-use configuration of secure provisioning project settings Enables direct communication with attached device for provisioning and programming. Supports generation of executable scripts for production use Manufacturing mode for simplified production line use     Secure Provisioning SDK (SPSDK) Secure Provisioning SDK (SPSDK) is an open-source development kit with its source code released on Github and PyPI. It contains a set of API modules for custom production tool development which requires more advanced secure provisioning flow. SPSDK enables connection and communication with NXP’s microcontrollers for the following purposes:   Generation of Secure Binary (SB) bootable images Security features configuration (CMPA, CFPA, Trustzone, secure bootloader, debug authentication, etc.) Generation and management of cryptographic keys and certificates Trust provisioning and secure programming through MCU Bootloader Debug authentication through J-Link, PEmicro and PyOCD debug probes   For more information about NXP development ecosystem for microcontrollers please visit: MCUXpresso Suite of Software and Tools https://nxp.com/mcuxpresso  

FRDM-MCXA153 FRDM-MCXN947    Hardware & Software To do this, surely you have to download the next software. MCU Link JTAG/SWD Debug Probe | NXP Semiconductors MCUXpresso IDE for NXP MCUs | Linux, Windows and MacOS | NXP Semiconductors | NXP Semiconductors About the hardware. FRDM-MCXN947 FRDM-MCXA153 MCU Link Firmware update. We will need the firmware to update the LPC55s69 on the board, the MCU Link firmware version 2.263 is compatible with the MCX. You may need the EVK connected to the computer under DFU mode, in the schematic of the EVK does not mention the DFU but has the named jumper of ISP [JP21] MCX - N or [JP8] MCX - A, sure you put the LPC55s69 in ISP, not the MCX, review the schematic below. MCX - N MCX - A When you have installed this version on your computer, go to the locations. ROOT: C:\nxp\MCU-LINK_installer_2.263\scripts Then open the CMD prompt console and run the script for CMSIS. The console asks if you have the appropriate jumper, if yes click enter again. If everything is right the message successfully will appear. Then in the MCUXpresso, you can see the debugger probe. Happy Debugging.