Abstract
This Knowledge Base text is intended to be an introduction for the MCX A14x/15x Architecture. Therefore, the content that is presented is described in a simplified way.
Contents
1. Introduction
2. Bus and Memory Architecture
3. MCX N vs MCX A series
4. MCXA SoC Power Domain Configuration
5. Clock Tree
6. Life Cycle and ROP State
7. Closing remarks
1. Introduction
The MCX is the new MCU for NXP generic-purposes microcontrollers.
Its portfolio offers a comprehensive selection of Arm® Cortex®-M based MCUs offering expanded scalability with breakthrough product capabilities simplified system design, and a developer-focused experience thought the widely adopted MCUXpresso suite of software and tools.
Particularly, the MCXA series MCUs expands the MCX Arm® Cortex®-M33 product offerings with multiple high-speed connectivity, operating up to 96 MHz, serial peripherals, timers, analog and low power consumption.
This device has following target applications:
- Consumer and industrial IoT
- Industrial Communications
- Smart Metering
- Automation and Control
- Sensors
The following figure shows a top-level organization of the modules within the chip organized by functional category.
Figure 1. Features block diagram
2. Bus and Memory Architecture
The memory system of the device includes SRAM, ROM, internal flash, and external memory.
The following figure shows the Bus matrix block diagram of this chip. Where there are three bus initiators (CM33, DMA and USB FS) which to access to different slave ports thought a Multilayer AHB bus matrix. ROM, Flash and RAMX0/1 share the same slave port. RAMA0/1 share a second slave port. And the third slave port is used to access to the peripherals.
Figure 2. Bus matrix block diagram
The Bus matrix block diagram has de following features:
- CM33
- Max speed is 96MHz
- Does not include MPU, FPU, DSP and Trustzone
- Cache
- 4KB LPCAC on CM33 code bus
- 8-way, 2-set-associative design based on 256-byte superpages. The access to flash can be cached.
- Write through
- Flash
- Up to 128KB flash.
- Line buffer and prefetch buffer
- IFR0 sector0 is CMPA region
- Memory Block Checker (MBC) is used to control the access permission
- Swap
- RAM
- SRAM is divided into Code TCM and System TCM:
- CTCM: Mapped to CM33 code bus space
- RAM X0: 8 KB 32-bit RAM
- RAM X1: 4 KB 32-bit RAM
- Can only be used as code RAM when LPCAC is disabled.
- CTCM: Mapped to CM33 code bus space
- SRAM is divided into Code TCM and System TCM:
-
-
- STCM: Mapped to CM33 system bus space:
- RAM A0: 8 KB 32+7-bit ECC RAM
- RAM A1: 16 KB 32bit RAM
- Execute permission is configurable
- STCM: Mapped to CM33 system bus space:
-
- Remap
- When remap is enabled, the access to RAM X0, will be remapped to the end of system RAM
3. MCX N vs MCX A series
The MCX N series have feature-rich on-chip accelerators and peripheral sets. Aimed at applications that need higher performance and fast features.
The MCX A series have several device options for a wide range of applications. Provides coverage for all applications requiring microcontrollers in entry-level target products.
The following table summarizes the main features of the MCX A and the MCX N series to compare their differences.
Table 1. Feature Comparison between MCX N and MCX A series
|
Description |
MCXN94x |
MCXA14x/15x |
Comments |
|
System |
2x DMA3, CRC, 2x WWDT, SPC, SCG, EIM, ERM, INTM, EWM, SYSCON, WUU, CMC, VBAT |
1x DMA3, CRC, WWDT, SPC, SCG, CMC, VBAT, EIM, ERM, SYSCON, WUU |
- MRCC in MCXA SYSCON is used to control peripherals’ clock select, clock divider and clock gating. - SPC and SCG programming model is forward compatible with MCXN. |
|
Security |
S50, PKC, PUF, TRNG, SM3, 2x GDET, Tamper, eFuse, ITRC, 2x CDOG, LVD/HVD, |
ROP (Read out protection), 1x CDOG, GLIKEY |
|
|
Clocking |
2x PLL, FRO144M, FRO12M, OSC48M, OSC32K, FRO16K |
FRO192, FRO12M, OSC48M, FRO16K |
- OSC48M min. frequency is reduced to 8MHz. |
|
Communications |
USB FS, 10x LP_FLEXCOMM, 2x FlexCAN, 2x SAI, 2x I3C, FlexIO, 2x EMVSIM |
USB FS, 2x LPSPI, 3x LPUART, LPI2C, I3C |
- LPSPI/LPUART/LPI2C are compatible with LP_FLEXCOMM. FIFO depth in MCXA is 4, and MCXN is 8. - I3C is new version in MCXA. It is compatible with MCXN - USB FS doesn’t support USB DCD in MCXA. |
|
High Speed Interface |
USB HS, FlexSPI, SDHC, ENET, eSPI, SPI Filter LPSPI (LP_FlexCOMM) |
LPSPI |
|
|
Timers |
2x FlexPWM, 2x QDC, 5x Ctimer, SCT, uTimer, OS Timer, RTC, 2x LPTMR, MRT |
1x FlexPWM, 1x QDC, 3x Ctimer, SCT, uTimer, OS Timer, Wakeup Timer, LPTMR |
- FlexPWM and Ctimer support up to 192MHz clock - 3 Sub Modules in FlexPWM of MCXA - QDC is a new design, but compatible with MCXN |
|
Analog |
2x 16bit ADC, 3x DAC, 3x CMP, 3x OPAMP, VREF, TSI |
1x 12bit ADC, 2x CMP |
- The ADC MCXA is single ended ADC, with single sample/hold circuit. Supports up to 4Msps in 12bit mode. |
|
Regulators |
DCDC, SYS_LDO, CORE_LDO, VBAT, SRAM_LDO OD/SD/MD RUN Mode |
CORE_LDO, SRAM_RET_LDO |
|
|
Power Mode |
RUN Mode: OD/SD/MD LP Mode: Sleep/DS/PD/DPD/VBAT |
RUN Mode: SD/MD LP Mode: Sleep/DS/PD/DPD |
|
|
IO |
6 rails, 124 GPIO, 100M/50M/25M IO |
2 rails, ~52 GPIO, 50M/25M IO High Drive IO, 5V Tolerant IO |
|
|
NEW |
MODIFIED |
|
New and modified features are highlighted. And as it can be seen, most of the features of the MCX A are compatible with the MCX N.
4. MCXA SoC Power domain configuration
The following figure introduce in a simplified way the Power Architecture block diagram of the MCX A. Where it can be seen that consist in three power supplies (VDD, VDD_ANA and VDD_USB) to power system and peripherals.
Figure 3. Power Architecture
VDD is the main supply which powers SYSTEM Domain, PMC, LDO_CORE and IO. At the same time CORE_MAIN Domain is supplied by LDO_CORE. VDD_ANA supplies ADC. And VDD_USB supplies USB FS PHY.
Power Architecture has the following features:
Run Mode
- SD mode with 1.1V VDD_CORE, 96MHz max.
- MD mode with 1.0V VDD_CORE, 48MHz max.
Low Power Mode
- Sleep Mode
- DS Mode
- PD Mode
- CORE_MAIN domain and RAM are retained in different voltage
- DPD Mode.
- CMC and SPC control the LP mode, which is compatible with MCX N
RAM Retention
- 3 RAM retention groups, which can be retained independently
- RAM X0 and RAM X1
- RAM A0
- RAM A1
- All RAM can be retained down to DPD mode
- RAM retention control logic is implemented in SPC
Power Sequence
- VDD and VDD_ANA must be ramp up same time with same level
Voltage Monitors
- POR on VDD
- LVD and HVD on VDD
- LVD on VDD_CORE
- VDD_USB detector
The following figure shows the Power Mode Transition block diagram. After POR the chip enters in Reset, when it exits from Reset the chip enters Active Mode. By performing Active Mode, it is able to enter all Low Power Modes. In Sleep and Deep Sleep Modes, it is possible to return directly to Active Mode. Meanwhile, to exit from Deep Power Down Mode, a Reset must be performed.
Figure 4. Power Modes Transition
5. Clock Tree
The following Figure shows a high level of Clock Architecture block diagram. In the left of the block diagram there are the on-chip clock sources, meanwhile in the right there is the distribution of the clock signals that clocking the systems and peripherals of the chip. The SCG controls FRO192M, FRO12M and SOSC clock sources. VBAT implements the 16 kHz internal clock source. And the MRCC provides on-chip modules their own dedicated MRCC bits for clock gating, reset control and configuration options.
Figure 5. Clock Architecture
The Clock Architecture has the following features:
Clock Source
- FRO192M. Outputs 192/96/48MHz
- FRO12M. Outputs 12MHz and 1MHz.
- SOSC. Supports 8~50MHz
- FRO16K. Output 16.384KHz
Clock Management
- Overall clock architecture is same with MCXN
- SCG and VBAT control clock generators
- MRCC in SYSCON controls clock mux and clock divider of the system and peripherals.
6. Life Cycle and ROP State
The following Table summarizes the Life Cycle State model and the Read Out Protection (ROP), which are designed to protect customer code and data from reading from the device internal flash. There are different levels of protection in the system, so that access to the on-chip flash and use of ISP can be restricted. Also, the life cycle state of the device determines the debug access and ISP command availability.
Table 2. Life Cycle and ROP
|
Life Cycle State |
ROP State |
Debug Port Status |
Debug Mail Box Command ISP Command |
|
NXP_PROVISIONED OEM_OPEN OEM_FIELD_RETURN NXP_FIELD_RETURN |
ROP0 ROP_STATE = 0xFFFF_FFFF ROP_STATE_DP = 0xFFFF_FFFF |
- Disabled by default - Enabled by Bootloader |
Full command |
|
OEM_CLOSED |
ROP1 ROP_STATE = 0x0000_0003 ROP_STATE_DP = 0x0000_0003 |
- Disabled by default - Not enabled by Bootloader - Debug configure register is not locked |
Reduced command |
|
ROP2 ROP_STATE = 0x0000_0001 ROP_STATE_DP = 0x0000_0001 |
- Disabled by default - Not enabled by Bootloader - Debug configure register is locked |
Reduced command |
|
|
OEM_NO_RETURN |
ROP3 ROP_STATE = 0x0000_0000 ROP_STATE_DP = 0x0000_0000 |
- Disabled by default - Not enabled by Bootloader - Debug configure register is locked |
No command |
|
BRICKED |
Other value |
- Disabled by default - Not enabled by Bootloader - Debug configure register is locked |
No command |
NXP_BLANK and NXP_FAB are NXP states that are not available for customers. NXP_PROVISIONED, OEM_OPEN, OEM_FIELD_RETURN and NXP_FIELD_RETURN are initial customer development states after leaving NXP manufacturing. OEM_CLOSED is the customer in-field application state, with ROP protection. OEM_NO_RETURN is the customer in-field application state, with ROP protection which prevents use of field return. And finally, BRICKED is the end-of-life state to prevent device use.
7. Closing remarks
- The MCX A series is based on the Arm Cortex-M33 operating at up to 96 MHz.
- It is scalable and easily migrated between N and A series given that peripherals and memories are very similar.
- The main on-chip memories are a Non-Volatile Flash memory with ECC and a RAM with ECC and Self-Test.
- Enhanced peripherals are designed with specific use cases in mind. This gives the applications a lot of focus on what they need.
- Improved Read Out Protection is built into the hardware designed to protect customer code and data from unauthorized readings.
- This device provide great flexibility and multiple options for the user to achieve low-power consumption with memory retention.
- Comprehensive serial communications included in the MCX A allow to interact with various components in customer applications.
- The analog integration selection within the MCX A also provides real-time response to the outside world, including ADC, CMP and temperature sensor.
- Utilize MCUXpresso software and tools to optimize, ease and help accelerate your embedded system development with a development suite that includes device configuration tools, drivers and middleware, multiple IDEs and a secure provisioning tool.
