In the LS1028ARDB, SPI is not enable, some customers need to enable this interface to debug their device and some customer maybe enable this device but the SPI sequence would be some uncertain error which will delay their plan. In this documents, will introduce how to enable the SPI3 on the LS1028ARDB, and use a SPI tools in the LSDK to help customer debug their SPI device in the initial stages of debugging.

Compile kernel in the ls-5.15.71-2.2.0_distro In the LLDPUG_RevL5.15.71-2.2.0, it seems when do some reconfiguration in the kernel, rootfs should be repack to finish the change. Here will generate kernel without repack the roofts in the Linux host machine just compile the kernel.

The u-boot in SDK2.0 has a bug on SGMII2.5 support. Need to add the patch.

Follow these steps to update DPAA2 MC firmware and DPC images in QSPI flash, if you are booting LS1088ARDB from the QSPI flash memory.  qixis_reset boots the board from QSPI flash0 (aka bank0) and qixis_reset altbank boots the board from QSPI flash1 (aka bank4). “sf probe 0:1” means that the alternate bank will be written to. So if you boot from flash0, then enter sf probe 0:1, the commands that follow will program flash1. Prerequisites Linux machine. It is recommended to install Ubuntu 18.04 on the Linux machine. Obtaining MC firmware Download the prebuilt MC firmware image from the git repository: https://github.com/NXP/qoriq-mc-binary/tree/integration/ls1088a Obtaining DPC image Clone mc-utils repository and compile the DPC image. git clone https://source.codeaurora.org/external/qoriq/qoriq-components/mc-utils cd mc-utils/ git checkout LSDK-18.09 make -C config/ The compiled dpc.0x1D-0x0D.dtb is available at /mc-utils/config/ls1088a/RDB/. Flash MC firmware image on LS1088ARDB QSPI flash In U-Boot, boot from flash0, program flash1:  

LS1043ARDB version updated because we replaced the Nand Flash with different page size one as the old one is obsolete. Version update information FA version Nand flash program by CodeWarrior Nand Flash firmware bring up files Boot Mode setting

Issue description. The CodeWarrior ®  TAP enables target system debugging via a standard debug port (usually JTAG) while connected to a developer's workstation via Ethernet or USB. This the hardware debug tool(JTAG debug tool) to debug the DN MPU. You could find the tool from below link https://www.nxp.com/design/design-center/development-boards-and-designs/CW_TAP To debug the Layerscape MPU, should select CWH-CTP-BASE-HE and CWH-CTP-CTX10-YE In fact, the CWH-CTP-CTX10-YE will adapt the different signal definition, one connector will be insert to the CWH-CTP-BASE-HE, and another one(totally 10 pins) will be used to debug the Layerscape MPU. You could find the definition of the JTAG connector(CWH-CTP-CTX10-YE, 10pins) on the Layerscape board. Pin 10 (SRST)is the signal of this documents to should add workaround.     In the CodeWarrior TAP Probe User Guide, the SRST(SRST_B) is Open-drain. So the voltage of this signal should be decided by the pull-up voltage connect to it. See the schematics part below, pin 10 (JTAG_RST_B) should be 1.8V, but in fact it’s not.   The test signal will be exceed 1.8V to about 2.6V.   If you connect this pin directly to the Layerscape MPU, it will violate the SPEC of the VIN. Workaround. Workaround for the user would be to use an external circuit (level shifter/limiter) for the affected signal(s). level-shifter/limiter CWTAP <=> probe tip <=> (level-shifter/limiter) <=> target Please refer to FRWYLS1046A-PA,  use the AND gate 74AUP1G11GW similar components which the Overvoltage tolerant inputs to 3.6 V.     Logic Device Customer could also refer to LS1046ARDB CPLD LCMXO1200C-3FTN256C and LX2160ARDB CPLD EPM2210F256C5N, even the CPLD IO Voltage is 1.8V, no issue with 2.6V input on 1.8V IO ports.    

When customer’s ethernet PCS could not link up, this article will give a guide how to debug it step by step based on the T1024. Many ethernet is configured by the SerDes, so how to confirm the link error is caused by the SerDes or the PCS itself. This article will give some clues. Serdes Lane&pins First check which SerDes lane the you are using, please confirm the SerDes land in the QorIQ T1024 Reference Manual. Such as configuration below, the user case set the SRDS_PRCTL_S1=0x05B in the RCW[128:136], the application will utilize the SGMII.m1 and SGMII.m2. This article will consider SGMII.m1 as an user case, now the SGMII will in the Frame Manager, MAC1. Check the SerDes Lane Assignments to confirm the Lane of the SerDes, for the SGMII.m1, the specific lane pins name would be SD1_TX3P/N and SD1_RX3P/N. it could be recognized as Lane 3. MAC number is not related to the Serdes lane number, should confirm the specific table to get the pins. Any hardware test with this ethernet should related the pins, see the component pin number below. You could test the eye diagram of RX pins of this Lane to confirm if the frequency is correct. if you set this Lane to SGMII 1.25G, you could confirm the speed is set correctly by the eye diagram. Eye diagram above, just show the speed of the SerDes. That is very important when loopback correctly, but could to connect to other device. How to confirm the SerDes link up Please find the Lane register in the QorIQ T1024 Reference Manual. In this user case it’s Lane 3, so should read out the Lane 3 registers to confirm if the SerDes Lane 3 work well. Such as below: # Lane 3 md.l 0xFFE0EA8C0 1 - aa611080 # LN3GCR0 md.l 0xFFE0EA8C4 1 - 101c4019 # LN3GCR1 md.l 0xFFE0EA8CC 1 - 00002800 # LN3SSCR0 md.l 0xFFE0EA8D0 1 - 0f0fc01f # LN3RECR0 md.l 0xFFE0EA8D4 1 - 0f0f0fa8 # LN3RECR1 md.l 0xFFE0EA8D8 1 - 00003006 # LN3TECR0 md.l 0xFFE0EA8E0 1 - 39000400 # LN3TTLCR0 md.l 0xFFE0EA8E4 1 - 00000000 # LN3TTLCR1 md.l 0xFFE0EA8F4 1 - 00000000 # LN3TCSR1 md.l 0xFFE0EA8FC 1 - 04000000 # LN3TCSR3   SerDes_LNnTCSR3 is an important debug test register, the CDR_LCK is to check if the CDR locked or not. CDR_LCK=0 means a valid bit stream is not detected. As a test, you could put the lane in loopback mode LN2TCSR3[LPBK_EN]=01. The CDR should lock in digital loopback mode (internal loopback). If not, there could be an issue with the device itself. So, if you could set the LPBK-EN to “01” Loopback Mode, it will set the SerDes’s own TX and RX signals in Loopback Mode to exclude external signals, then check the CDR_LCK again, if it’s 1, then SerDes itself works well. Anyway, CDR_LCK should always be set. In the “md.l 0xFFE0EA8FC 1 - 04000000 # LN3TCSR3”, the CDR_LCK=0, suspect the SerDes level issue. The normal status should be: => md fe0ea8fc 1 fe0ea8fc: 08000000 How to confirm the PCS link up The MAC and PHY registers should get the details from the T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual Find the offset address in the DPAARM. For the SGMII MAC address should be offset+0x1000. Follow the 6.5.4 MDIO Ethernet Management Interface usage in the T1024DPAARM to read the MDIO registers. In this application, SGMII1, MAC1, you could find the MAC1 address would be FM1_mEMAC1: 4E_0000, so FM1_mEMAC1 MDIO registers would be 4E_1000h. In the user case, the protocol is SGMII, should follow the 6.5.4.3 Clause 22 Read Flow in the T1024DPAARM. 6.5.4.3 Clause 22 Read Flow 1) Wait for MDIO_CFG[BSY] = 0. 2) Write MDIO_CTL with proper PHY_ADDR and REGISTER_ADDR and with bit 16 set. 3) Wait for MDIO_CFG[BSY] = 0. 4) If the addressed PHY did not respond then MDIO_CFG[MDIO_RD_ER] is set. Otherwise read MDIO_DATA value. In this user case, should read the MDIO_SGMII_SR, you could find the register definition in the QorIQ T1024 Reference Manual, 30.5.5 1000Base-KX PCS MDIO Memory Map/Register Definition The key bits would below: Here the user case result: When you read MDIO_SGMII_SR, please use manual input that can meet the delay time requirement. If you could not input manually, please follow the flow, " Wait for MDIO_CFG[BSY] = 0" before read MDIO_DATA value. Read SGMII1 MDIO Registers === Serdes Test 1 === 0xFFE0EA8FC value: 0x08000000 Dump PCS0 Registers 0xFFE4E1030-0xFFE4E103C: 0x40001408 0x00000000 0x00001340 0x00001340 Select 0x8002 ,devmem 0xFFE4E1034 32 0x8002 Read: 0x00000083 Select 0x8003 ,devmem 0xFFE4E1034 32 0x8003 Read: 0x0000E400 Select 0x8001 ,devmem 0xFFE4E1034 32 0x8001 Serdes0 Status: 0x00000029 Select 0x8001 devmem 0xFFE4E1034 32 0x8001 Serdes0 Status: 0x0000002D Select 0x8001, devmem 0xFFE4E1034 32 0x8001 Serdes0 Status: 0x0000002D The first time, it’s not link, LINK_STAT is 0(0x00000029), and then it’s turn to 1(0x0000002D). Now the PCS link up and the HW loopback checking is completely.