Test Environment: FRDM-KL43Z Rev. A MCUXpresso IDE v10.2.0 MCUXpresso SDK for FRDM-KL43Z V2.4.1(2018-06-18) Create new project in MCUXpresso IDE select [New project...], there will pop the SDK Wizard panel, then select [frdmkl43z]: Then, click [Next] will enter into [Configure the project] panel, we can set the [Project name] and select [flexio_i2s] in [driver]: Click [Finish], the new project was created. In general, the project is based on [hello_world] project with board default console available. In [Project Explorer], we could find the <fsl_flexio_i2s.c> & <fsl_flexio_i2s.h> & <fsl_flexio.c> & <fsl_flexio.h> files in drivers folder: Edit the code The application note AN5397 detailed introduce how FlexIO emulate I2S bus communication. The MCUXpresso SDK <flexio_i2s> driver using the AN5397 showed second solution to use two timers and two shifters. Please check here to get more detailed info. The I2S signal was below, we need to use four FlexIO pins to provide: BCLK, Fss, TxData & RxData. In <pin_mux.c> file, it need to config pin function, we use PTD7 pin provide I2S BCLK clock; PTD6 pin as I2S Frame_sync pin; PTD5 pin as Tx data pin; PTD6 pin as Rx data pin; In <frdmkl43z_flexio_i2s_interrupt_tx.c>,  config flexio_i2s and config the audio frame format: Please check attached source code for the detailed project info. Test result From the actual measured I2S signal, it shows the 8 bytes was sent out:

主板原理图。

           This is a demo of NFC device to read and write the contactless card. Kinets K60 tower board and NXP PN512 board are used for this test enviroment. These connected pins from K60 tower board to PN512 RF board are listed as below:   SPI1:     SPI1_SIN : PTE1/SDHC0_D0     SPI1_SCK : PTE2/SDHC0_DCLK     SPI1_SOUT : PTE3/SDHC0_CMD     SPI1_PCS0 : PTE4/SDHC0_D3     Reset:     PTB9   External interrupt:     PTA26         Because the SPI1 port is used as the host interface of pn512, it is necessary to enable the SPI1 driver in the user configuration file of MQX.           To open the project file in the /build folder with CW10.5.    And the PSP and BSP libraries had to be built before test image is built, as they are needed in this test project.   The following diagram shows the serial numbers and block data of reading from the test card of Mifare one.

Hello all,      So, this time there is a query on implementing IRDA communication by bit banging the GPIOs. So, I come up with an experiment to do so. Before that, why bit banging when KE02 supports IR communication right away by using FTM at TX and ACMP at RX? something similar to this Implementing infrared functions on UART0 with FRDM-KE02Z platform.        The answer lies in the waveform attached. In the code from the above discussion, the PWM modulation is performed on FTM channel for transmission, while the communication that customer required was different and the waveform required is the one attached.                                                                                           Note that the IRDA transmitter on FRDM-KE02Z is connected to UART0. But, in the attached code, UART0 is not configured for IRDA_TX. while ACMP is used for RX.      This post is intended to be a reference to those who want to implement IRDA with 3/16th bit width by bit banging.      Here is the schematic snapshot of the FRDM-KE02.   There are 2 sets of codes attached. 1. FRDM_KE02_singleboard_IRDA_BITBANGING_TX_RX - IRDA on a single board. 2. FRDM_KE02_interboard_IRDA_BITBANGING_TX_RX - IRDA between 2 boards.   To run a single board demo, the orientation of IRDA Transmitter and IRDA receiver is already taken care as both are on the same board. But, to run the second demo, the orientation is supposed to be something like this.   Both the demos are configured for 9600baud to communicate with PC. And the IRDA communication is at 2400baud.      The figure in page 13 of this document is referred while development. http://www.vishay.com/docs/82513/physical.pdf                                                                            Transmission - 1. The bit width is calculated depending on the required IRDA baud and PIT1 modulo is adjusted accordingly. There are 3 MOD values initialized one after the other to generate required IR frame. 2. The data to be transmitted is sent over the HyperTerminal @ 9600baud. This data is accordingly transmitted on PTB1.      The green waveform in the below oscilloscope snap is the IR frame from the above picture. The data being sent is 'e', the hex value of which is 0x65 which can be made out from the waveform. 0x65 is 0xa6 in reverse since LSB is sent out first in the IRDA protocol[The first logic high is the start bit. In IRDA transmission, logic low is data '1' and logic high is data '0'].                                                                                      Reception - 1. ACMP0 is configured to generate interrupts on either the rising edge or the falling edge. 2. The falling edge of the start bit triggers ACMP. 3. The logic received on PTA1 is decoded to arrive at the received data. 4. The falling edge on ACMP channel decides logic 0 and the PIT0 interrupt decides the logic 1.      The below waveform is the one probed at PTA1.                                                                     Thanks, Pramod TM

This is a Processor Expert project created by CodeWarrior for MCUs v10.6 which implements the charge-discharge time of a RC circuit for measuring capacitance. The charge-discharge sequence is performed by TPM0 operating in PWM mode, while the time is measured by TPM1 operating in Input Capture mode. A 100K ohm series resistor is being used, and the result is expressed on nF. It is also using the LCDHTA component from Erich Styger for showing the measurements on a 16x2 LCD, connected to the FRDM-KL05Z through a proto shield. The project is attached, and the pictures shows the measurements of three different capacitors: 10nF, 47nF and 1uF.

Hello Freedom community users Bheema has posted on the Element14 community a very clear tutorial (accessible following the link below) to create from scratch a basic project example featuring the SLCD of the FRDM-KL46Z with Processor Expert. Freescale Freedom development platform: [FRDM-K... | element14 Those steps should be very useful to create your own project featuring SLCD display and better understand the constraints of this peripheral. Happy SLCD Displaying Greg

Hello Kinetis World, I just wanted to take this opportunity to share the press release for our newly announced WLCSP device.         http://finance.yahoo.com/news/thin-blade-grass-freescale-newest-120000684.html The Ultra Thin CSP, MK22FN512CBP12R, is equivalent to the standard height CSP, MK22FN512CBP12R.  Therefore, from Therefore, from a software enablement perspective, the MK22FN512CAP12 device can be selected as shown in the attached Processor Expert screenshot.  We're looking forward to seeing what amazing things you can accomplish using Kinetis technology!      

1.jicheng0622-AET-电子技术应用 2.wuyage-AET-电子技术应用 3.fanxi123-AET-电子技术应用

This file describes how to install KSDK, is easy and simple with images and descriptions step by step, so you wont have problems with the installation.

On NXP website we had provide an application note " Kinetis-M Two-Phase Power Meter Reference Design" which can been found here: http://www.nxp.com/docs/en/application-note/DRM149.pdf  This is really a quite useful solution for 2-Phase Power Meter design. From the schematic, there has a LCD display. Many customer sent email to ask for the datasheet of this LCD display(GDH-1247WP). Yes agreed, it is really difficult to find it. ( Even from the google.) I am attaching the data sheet for the segment LCD here for customer to make reference.

El programador USBDM es una interfaz de programación y depuración para los microcontroladores Freescale, existen varias versiones de esta herramienta, el programador MantaRay USBDM está basada en la versión para los microcontroladores HCS08(BDM) y Kinetis (SWDIO). Toda la información acerca de este proyecto puedes encontrarlo en http://usbdm.sourceforge.net/index.html BDM (Background debug mode) El puerto de programación BDM es una interfaz de programación desarrollada por Freescale para los microcontroladores HCS08 (8 bits) y Coldfire V1 (32 bits). Las características más sobresalientes sobre este puerto de programación es que solo utiliza un pin de programación (BKGD). Además de permitir la programación de la memoria flash, también permite el "debug in circuit" esto quiere decir que podemos depurar nuestro codigo en tiempo real a través del software Codewarrior. SWDIO Es la versión minima del JTAG para los microcontroladores Kinetis (Cortex ARM 32 bits) en la cual solo utiliza una linea de comunicación (SWDIO) y una señal de reloj (SWCLK). Este puerto esta en los Cortex M0 como son KL01, KL02, KL03, KL1x,KL2x,KE02,KE04 y KE06. El programador MantaRay USBDM permite la programación y la depuración de los microcontroladores de Freescale de la gama de 8 bits y 32 bits. Shrimp El complemento perfecto para el programador MantaRay USBDM es Shrimp, una pequeña tarjeta que tiene el tamaño exacta de un integrado con montaje DIP28 600mil, la cual, la hace una herramienta flexible, al hacer prototipos en una protoboard, y después en un prototipo final. La tarjeta Shrimp es compatible con los microcontroladores de 8 bits MC9S08PA16 y de 32 bits MKE02Z16, los dos totalmente compatibles en pines y periféricos. MC9S08PA16 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across temperature range of -40 °C to 105 °C – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 16 KB flash read/program/erase over full operating voltage and temperature – Up to 256 byte EEPROM; 2-byte erase sector; program and erase while executing flash – Up to 2048 byte random-access memory (RAM) – Flash and RAM access protection MKE02Z16 • Operating characteristics – Voltage range: 2.7 to 5.5 V – Flash write voltage range: 2.7 to 5.5 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 40 MHz ARM® Cortex-M0+ core and up to 20 MHz bus clock – Single cycle 32-bit x 32-bit multiplier – Single cycle I/O access port • Memories and memory interfaces – Up to 16 KB flash – Up to 256 B EEPROM – Up to 2 KB RAM Más información técnica la puedes encontrar en el siguiente link http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=KE02&nodeId=01624698C90DE4 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=S08P&nodeId=01624684491437EDDD Muy pronto mas adelantos de este proyecto

1. Overview BLE beacon is a common use of low power Bluetooth and it broadcasts advertisement at some interval. Freescale BLE beacon demo use Freescale Kinetis KL16 low power MCU and EMC EM9301 Bluetooth controller to implement a beacon reference design. Freescale BLE beacon features low power consumption of an average cost of 50uA with 600ms interval. Freescale Kinetis KL16 coordinates with EM9301 through SPI interface. View attachment to learn more

Customer requirement and making it happen This hands-on test is coming with the true customer requirement. Customer designs the battery powered device with SLCD display and lowest power consumption is the key requirement. Customer considers the KL43 and wonder the power consumption data about RTC & SLCD modules. So there with below requirements about the test: Run the RTC and SLCD in the lowest possible power mode Display time at SLCD with [00:00] and update every minute via RTC interrupt               One button shall turn on/off the SLCD display Measure the KL43 power consumption data KDS IDE with KSDK V2.0 software According to above requirement, which low power mode should be selected? RTC and SLCD modules should work at this low power mode. From the KL43 reference manual table 7-2 [Module operation in low power modes] with below info:      5. In VLLS0 the only clocking option is from RTC_CLKIN.      7. End of Frame wakeup not supported in LLS and VLLSx. RTC and SLCD modules could work at VLLS1 low power mode with Async operation. Using VLLS1 low power mode, the RTC and SLCD module clock could select OSC32KCLK with below clocking figure: KL43 wake up from VLLS1 low power mode following wake up reset and the software will check the system reset status register to check what kind of reset happens and print related info. LLWU module is used as VLLS1 lower power mode wake up module with two wake up source, one is RTC Alarm interrupt, the other one is PTC3 (SW3). The Reset pin (SW2) also could wake up the VLLS1 low power mode. Test environment introduction Hardware platform using FRDM-KL43Z board with below feature: MKL43Z256VLLZ4 MCU (48 MHz, 256 KB flash memory, 32 KB RAM, 16 KB ROM Dual role USB interface with mini-B USB connector OpenSDA Four-digit segment LCD module Capacitive touch slider Ambient light sensor MMA8451Q accelerometer MAG3110 magnetometer 2 user push buttons Battery-ready, power-measurement access points Arduino R3 compatibility Software platform bases on KSDK V2.0 for FRDM-KL43Z board, which could be downloaded from kex.nxp.com. Attached demo software default path is: C:\Freescale\SDK_2.0_FRDM-KL43Z\boards\frdmkl43z Test software code introduction Below is the software flow chart: Test result SLCD ON with power consumption 2.0uA SLCD OFF with power consumption 1.2uA

Hi, I have a project created by Processor Expert and CodeWarrior 10.2 for TWR-K20 demo kit. Becasue I have some problem to use the Processor Expert USB HID Keyboard Host of the USB stack 4.1.1, I need to change to add the non-PE USB HID Keyboard Host into the project. Can anyone tell me how to do it? It will be very appreciated to give me a simple 'PE' example project, and add the non-PE USB HID keyboard host stack. Thank you! Stanley

Example of integrating CMSIS3.20 into MQX4.0.x on the TWR-K70F120M (with floating point unit) using CW10.4 using the MQX4.0.2\mqx\examples\hello2 project. In the attached ZIP file (hello2twrk70f120m_CMSIS_FPU.zip) is a MSWord document detailing the steps used.  That document name is TWR-K70F120M_CMSIS_CW10.4_MQX4.0.x.docx. Regards, David

This file contains some codewarrior code examples migrated from the IAR examples in the sample code package available at the freescale webpage: blink_blue blink_red blink_rgb serial_test_19200 serial_test_115200 touch_toggle_leds Regards

Freescale Semiconductor is to demonstrate its Kinetis L series microcontrollers (MCUs) built on the ARM Cortex-M0+ processor at DESIGN West in San Jose, California, with alpha sampling due to start in the second quarter of 2012. Freescale  says the ability to demonstrate these devices is possible due to its  close partnership between ARM during the Cortex-M0+ core development  process and as a lead partner provided  input that helped ARM define and  develop the processor. The devices are slated for applications  such as domestic appliances, portable medical systems, smart meters,  lighting, power and motor control systems. "Our close partnership  with ARM throughout the design and development of their new core has  positioned us as the first MCU supplier to produce and demonstrate an MCU based on the Cortex-M0+ and continues our strategy of driving to  market new products based on the ARM architecture," said Reza  Kazerounian, senior vice president and general manager of Freescale’s  Automotive, Industrial and Multi-Market Solutions Group. Mike  Inglis, executive vice president and general manager of ARM’s Processor  Division, added "With the addition of the L series to their Kinetis  line, Freescale is creating one of the industry’s broadest, most  scalable ARM Cortex-M MCU portfolios, ranging from very low-cost,  entry-level products based on the ARM Cortex-M0+ processor, up to 4 MB,  200 MHz devices based on the Cortex-M4 processor." Manufactured  using Freescale’s low-leakage, 90 nm thin film storage (TFS) process  technology, the Kinetis L series will have a selection of on-chip flash  memory densities and analog, connectivity and HMI peripheral options. Upward  migration through the Kinetis portfolio is available via compatible Kinetis K series devices (built on the ARM Cortex-M4 processor) that  provide access to DSP performance and advanced feature integration. The  ARM Cortex-M0+ processor includes a reduced two-stage pipeline,  allowing faster branch instruction execution, single-cycle access to I/O  and critical peripherals, optimized access to program memory, linear 4  GB address space that removes the need for paging, reducing software  complexity and ensuring a more 8-bit-like user experience and a micro  trace buffer, providing a low-cost trace solution that allows faster bug  identification and correction without the need for additional I/O  resources. Freescale will demonstrate the ARM Cortex-M0+ core at its exhibition booth #1604 at DESIGN West , March 26-29 at the San Jose McEnery Convention Center.