Kinetis Microcontrollers Knowledge Base

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Kinetis Microcontrollers Knowledge Base

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Hi All, NXP provide a software driver library for Kinetis M devices, the KM bare-metal drivers. It includes support for peripherals and FreeRTOS. :smileyalert:NOTE: Before creating a new FreeRTOS project for KM devices you need to download the KM driver support package and install it. You can find the instructions HERE​. FreeRTOS new project creation The following instructions will guide you to generate a new project for Kinetis M devices with all the bare-metal drivers’ support. You can either select create a new project without FreeRTOS support or with it. In this case the instructions show how to create a FreeRTOS project for IAR 7.5. Go to template folder in the KM drivers package installation folder Run the make_project by Double clicking on it The make-project application guide the user to select the appropriate application. Select the IDE for new project support according to the application requirements. NOTE: The IDEs showed are only the IDEs that its support package is installed. The new project creation also manages the debug options for the project. Select the specific debug option for your new project. Select the KM variant you are using. NOTE: For KM34Z256 devices the default option is MKMxxZ256 and is selected automatically. The creation of the project supports creating linked or standalone projects: o   Create projects in driver’s subfolder: The project will be created in the path KMxxxSWDRV_Rx_x_x\build\supported_ide\projects and all the folders and files inside the project will be linked to the real location setting virtual folders in the workspace. In this case it will not be possible to move the project from that location, doing it will cause building problems. o   Create Standalone project: The standalone project option will let us select the new project location and will link the files to the actual project location. In this case the necessary source code will be copied to a new location. This options is recommended for versions control If option 1 is selected the project will be generated, you can check the project in the mentioned folder. If option 2 is selected following instructions need to be followed. Type the path that will contain the new project. In this path project files will be installed. Type project name and press enter. Project will be created and make_project window will self-close. Project folder structure looks like next: Open the IAR project by double clicking in the .eww file of the new project. FreeRTOS project structure This section will discuss the FreeRTOS default project and main.c file structure. Here a project created for IAR 7.5 is presented as an example. There are two main folders in a FreeRTOS application. The rest of the folders and files are the same for non-RTOS applications. freertos > contains all the FreeRTOS Kernel source code project > Contains files to configure definitions, FreeMaster usage and the main function. NOTE: The main function will be always contained in a file named project_name.c This is the structure of the project_name.c file: By default the main function contains the code to create and start two different tasks. Also, in the same file, the two tasks are defined. The main function initializes the application peripherals and create task A and task B. The xTaskCreate() function creates a new task and adds it to the list of tasks that are ready to run. The functions is defined as: pvTaskCode. Pointer to the task entry function. Tasks must be implemented to never return. pcName. A descriptive name for the task. This is mainly used to ease debugging. Max length defined by configMAX_TASK_NAME_LEN. usStackDepth. The size of the task stack specified as the number of variables the stack can hold - not the number of bytes. For example, if the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes will be allocated for stack storage. The stack depth multiplied by the stack width must not exceed the maximum value that can be contained in a variable of type size_t. pvParameters. Pointer that will be used as the parameter for the task being created. uxPriority. The priority at which the task should run. pvCreatedTask. Used to pass back a handle by which the created task can be referenced. After creating the two tasks the main functions calls vTaskStartScheduler() that starts the real time kernel. After calling the kernel has control over which tasks are executed and when. The task source code looks like the following: Tasks receive pvParameters parameter, this is the one that this passed when Task is created (refer to the pvPrameters in cTaskCreate function). Each task has an infinite loop, this means the task will run continuously but the RTOS schedules will the one deciding when each task will run according to priority. Default project can be modified by user adding tasks and using RTOS services to create application. If support for a different IDE is needed you just need to change follow the instructions decribed in FreeRTOS project creation and select the IDEs required by your application. References: FreeRTOS manual from THE TOOLCHAIN​ Hope information helps! Happy FreeRTOS coding! Regards, Adrian Cano NXP FAE
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As most of people familiar with FRDM-K64F which is a bit old but it is still a hot device in the market. This document focused on the ADC measurement to verify the deviation. In general, the sample code were modified /come with MCUXpresso SDK, which is an ADC polling example. ADC reading was done by two ways: 1) Polling the status register of ADC conversion complete flag until ADC conversion is done. 2) CPU core is in sleep right after ADC conversion is started by software trigger. Interrupt is generated when ADC conversion is done and CPU core wakes up by this interrupt. The value of ADC reading is measured 5000 times. And, it is averaged, also calculate max/min value. Finally, the standard deviation is calculated based on the 5000 measured value. PRINTF is a terminal console and print out by semi-hosting. Interrupt method or polling method can been selected by the define of INTERRUPT or POLLING. #define INTERRUPT 0   //ADC conversion wait for “INTERRUPT” should be defined to 1 #define POLLING 1   //ADC conversion wait for “POLLING” should be defined to 1
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      Kinetis SDK是针对于Kinetis系列MCU所做的软件开发套件,又称为KSDK。它由强大的外设驱动代码库,协议栈库与示例代码库等部分组成,能够简化和加快对于Kinetis 系列MCU的应用开发。另外,Kinetis SDK是免费的工具,而且所有的硬件抽象和外设驱动软件均开放完整源代码。目前最新版本为2.0,支持 Kinetis 主流MCU,随后会不断更新完善。对于SDK支持MCU的更新情况,可登陆以下KSDK的下载页面了解。       有关KSDK的更多信息可以从网址www.nxp.com/ksdk 获得。
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Kinetis E series MCUs target to applications where require high performance on EMC/ESD. With 5V power supply and robust IO design, Kinetis E series MCUs can help customer for a robust design. Here take a Microwave Oven demo as example, shares how to make a robust design with Kinetis E Series MCU, from hardware, software perspective.
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Today the universal motor is still widely used in home appliances such as vacuum cleaners, washers, hand tools, and food processors. The operational mode, which is used in this application, is closed loop and regulated speed. This mode requires a speed sensor on the motor shaft. Such a sensor is usually an incremental sensor or a tachometer generator. The kind of motor and its drive have a high impact on many home appliance features like cost, size, noise, and efficiency. Electronic control is usually necessary when variables speed or energy savings are required. MCUs offer the advantages of low cost and attractive design. They can operate with only a few external components and reduce the energy consumption as well as the cost. This circuit was designed as a simple schematic using key features of a Kinetis L MCU. For demonstration purposes, the Freescale low cost Freedom KL25z development platform was used. This application note describes the design of a low-cost phase angle motor control drive system based on Freescales’s Kinetis L series microcontroller (MCU) and the MAC4DC snubberless triac. The low-cost single-phase power board is dedicated for universal brushed motors operating from 1000 RPMs to 15,000 RPMs. This application note explains both HW and SW design with an ARM Kinetis L series MCU. Such a low-cost MCU is powerful enough to do the whole job necessary for driving a closed loop phase angle system as well as many others algorithms.        -Freedom development platform with universal motor drive board extension The phase angle control technique is used to adjust the voltage applied to the motor. A phase shift of the gate’s pulses allows the effective voltage, seen by the motor, to be varied. All required functions are performed by just one integrated circuit and a small number of external components. This allows a compact printed circuit board (PCB) design and a cost-effective solution. Learn more about the Kinetis L series Freedom Board Get the full application note in the link bellow:
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1.jicheng0622-AET-电子技术应用 2.wuyage-AET-电子技术应用 3.fanxi123-AET-电子技术应用
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Anis Jarrar, Freescale design engineer, explains how his team developed Kinetis and how the result of their "chasing nanowatts" concept resulted in a highly scalable, ultra low power MCU. 32-bit Kinetis MCUs represent the most scalable portfolio of ARM® Cortex™-M4 MCUs in the industry. The first phase of the portfolio consists of five MCU families with over 200 pin-, peripheral- and software compatible devices with outstanding performance, memory and feature scalability. Enabled by innovative 90nM Thin Film Storage (TFS) flash technologu with unique FlexMemory (configurable embedded EEPROM), Kinetis features the latest low-power innovations and high performance, high precision mixed-signal capability. Kinetis MCUs are supported by a market-leading enablement bundle from Freescale and ARM 3rd party ecosystem partners. http://www.freescale.com/kinetis
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1. CycloneMAX,    支持 Kinetis, ColdFire V2/V3/V4, Power MPC5xx/8xx, Qorivva MPC5xxx, DSC, MAC7xxx    PE Micro, http://www.pemicro.com/ 2. Flasher ARM     支持ARM公司全系列内核,包括传统的ARM7, ARM9和ARM11,已经新的Cortex-A, Cortex-M和Cortex-R系列,可以给目标板供电.    Segger, SEGGER - The Embedded Experts - Flasher ARM 3. Flasher Portable    支持ARM公司全系列内核,包括传统的ARM7, ARM9和ARM11,已经新的Cortex-A, Cortex-M和Cortex-R系列,电池供电,便携式烧写器.    Segger, SEGGER - The Embedded Experts-Flaser Portable 4. SmartPRO    支持 Kinetis, S12, S12X, ColdFireV2.    周立功,http://www.zlgmcu.com/ 5. MCP-104    支持飞思卡尔ARM based Microcontroller Kinetis.    祥佑科技(Micetek), http://www.micetek.com 6. 西尔特编程器,http://www.xeltek.com 7. 河洛编程器,http://www.hilosystems.com.tw
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[中文翻译版] 见附件 原文链接: https://community.nxp.com/docs/DOC-335320
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This hint will demonstrate how to verify ADC conversion rate (with oscilloscope) during testing phase.   Refer to the phenomenon descripted in"Figure 1. Voltage drops at ADC input during sampling process" of AN4373. If too large values is selected for the external RC components, serious voltage disturbances (voltage drops/peaks) at the ADC input (see Figure 1) can be observed. The disturbance at the ADC input in this case results from the basic principle of operation of the sample and hold (S/H) circuit inherent in a SAR ADC. Although we should avoid this happening, but it can be used to measure the ADC conversion rate with oscilloscope during testing phase.   According to the 'Table 30. 16-bit ADC operating conditions' of K64P144M120SF5, we can know that the max ADC conversion rate is 818.330 ksps. Here I create an example by using KDS3.2 with Processor Expert(See the attach file). After select same configuration according to that table, I got almost the same ADC conversion rate. The conversion time meet equation given in Reference Manual too. Now let's measure the ADC conversion rate on FRDM-K64F board with oscilloscope. After connected an external 1.5KΩ resistance, the value of external RC components is big enough to be observed. Below is the waveform observed with oscilloscope, the frequency between voltage drops at ADC input during sampling is about 818 ksps. This test result is consistent with the theoretical calculated value.
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Here you can find both the code and project files for the PWM project, in this example a single PWM channel belonging to the Flextimer 0 (PTC10/FTM_CH12) is enabled to provide a PWM signal with a 500ms period, the signal's duty cycle increases its period every 100ms, to visually observe the signal connect a led from the A5 pin in the J4 connector to GND (J3, pin 14). Code: #include "mbed.h" //PWM output channel PwmOut PWM1(A5); int main() {     PWM1.period_ms(500);     int x;     x=1;         while(1)     {         PWM1.pulsewidth_ms(x);         x=x+1;         wait(.1);         if(x==500)         {             x=1;         }     } }
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Here you can find the code and project files for the Interrupt example, in this example 2 KBI interrupts are enabled, one assigned to SW2 and another to SW3, during the main routine the blue led is turned on, when the interrupt routines are triggered the blue led is turned off and the red or green led blink once, the interrupt was configured to detect falling edges only. Code: #include "mbed.h" DigitalOut Red(LED1); DigitalOut Blue(LED3); InterruptIn Interrupt(SW2); void blink() {     wait(.4);     Red=1;     Blue=0;     wait(.4);     Blue=1;     wait(.4); } int main() {     Interrupt.fall(&blink);     Blue=1;     while (1)     {         Red=!Red;         wait(.4);     } }
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Hello Freedom community users Bheema has posted on the Element14 community a very clear tutorial (accessible following the link below) to create from scratch a basic project example featuring the SLCD of the FRDM-KL46Z with Processor Expert. Freescale Freedom development platform: [FRDM-K... | element14 Those steps should be very useful to create your own project featuring SLCD display and better understand the constraints of this peripheral. Happy SLCD Displaying Greg
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1.基于CMSIS-DAP的脱机编程工具         飞思卡尔的FRDM开发板都板载OpenSDA仿真器,该仿真器基于MK20DX128VFM5芯片,内部由Bootloader和app所组成,当用户按下Reset按钮后再插上USB接口,此时会进入Bootloader模式,此时PC端会出现一个名为Bootloader的可移动存储器,用户可以通过拖入预编译好的*.SDA升级app,更新v114版本的app后,重新插拔USB即可生效,此时会枚举出虚拟串口,仿真器以及MSD的可移动存储器。Bootloader占用了MK20DX128VFM5内部从0开始到0x5000的地址,App从0x5000地址开始。        CMSIS-DAP(mbedmicro/CMSIS-DAP · GitHub)是ARM公司的一个开源项目,它提供了一个基于Web的开发环境(mbed | welcome), 开发环境提供了基于C++的开发库,用户可以通过Web编程,然后下载编译好的bin文件,通过CMSIS-DAP烧写到FRDM开发板中。CMSIS-DAP与OpenSDA类似,也是由Bootloader和app所组成,最大的区别是CMSIS-DAP的Bootloader占用的地址为0x0~0x8000。        由于CMSIS-DAP是Apache License开源的,通过修改其Bootloader代码可以比较容易的做出一个脱机烧写器参考。        1. 添加SWD的访问接口。        2. 修改链接文件,默认Bootloader是运行在0地址上的,而实际编程工具最好运行在0x5000或者0x8000这两个地址上,这样不需要通过仿真器对于MK20DX128进行编程即可更新其内容,同时也可以轻松在仿真器及烧写器间进行切换。        3. 修改MSD烧写文件的地址,默认Bootloader是烧写从0x5000或者0x8000开始的地址,而这个地址现在放的是脱机烧写器代码,所以需要向后移动到0x10000,并将目标文件大小存放在0x1F800地址上。脱机烧写器由于将目标文件存放在K20芯片内部,所以受到K20内部flash大小的限制,只能烧写目标文件小于60K。        4. 添加编程算法工程,由于目标芯片内部的flash需要不同的驱动,所以可以将他们生产的算法代码先放到K20内部0x1FC00的地址上,烧写器开始工作时,先将编程算法通过SWD下载到目标文件的RAM中,并修改目标芯片的SP PC指针,让其运行。编程算法与烧写器的运行程序通过RAM进行交互。 参考代码下载地址: hudieka/OpenSourceOfflineProgrammerTools · GitHub 具体使用方法可以参考附件:
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客户要求:K60 100MHz芯片作为SPI主机读取片外SPI Flash存储器内容(SPI Flash器件数据准备完成会触发K60 GPIO中断),要求在130~150微秒之间读取九个不连续地址上的数据,每个地址需要读取4个字节,SPI波特率为5MHz。读取SPI Flash存储器,需要使用读取命令(1个字节)外加地址(2个字节)。换言之,每读取一次K60需要发送7个字节(1字节读取命令+2字节地址+4字节空读数据)。同时要求减少内核负担。 Customer requirement: Use K60 100MHz product as SPI master communicate with external SPI Flash device (When data ready, SPI Flash device will trigger K60 GPIO interrupt), it need to read data from 9 discontinuous address, each address read 4 bytes within 130~150us. SPI  baud rate is 5MHz. Read data from SPI Flash, it need SPI master send 1byte read command and 2bytes address. In another word, K60 need to send 7bytes(1byte read command+2bytes address+4bytes dummy read) 9times within 130us. SPI communication baud rate is 5MHz. It also require to reduce core work load. 实现方法:使用DMA模块,其中一个DMA通道1用来装载SPI传输TX数据(触发源为SPI TFFF符号,SPI FIFO可装载),另外一个DMA通道0用来接收SPI数据(触发源为SPI RFDF符号,SPI 接收FIFO非空)。通过使用DMA引擎可以自动发起SPI传输,减少内核在SPI传输过程中的干预,达到降低内核工作负荷的效果。SPI模块采用中断方式。 Reality way: Use DMA module, DMA CH0 loads data for SPI transmit, DMA CH1 stores data for SPI receive.  DMA triggered by SPI module and SPI module works in interrupt way. 测试平台:TWR-K60D100M, TWR-MEM, IAR ARM Workbench V6.60 TWR-MEM板子提供SPI Flash设备(AT26DF081A),可以通过TWR-K60D100M SPI2模块进行访问。 Test platform: TWR-K60D100M ,TWR-MEM , IAR ARM Workbench V6.60 SPI Flash AT26DF081A on TWR-MEM board, which could be accessed by TWR-K60D100M via SPI2 module. 测试场景一:读取AT26DF081A设备ID信息 Test scenario 1:  Read device ID AT26DF081A设备提供查询设备ID命令0x9F,返回4个字节设备ID信息(0x1F,0x45,0x01,0x00)。K60作为SPI主机发出查询命令,之后执行4次空写入操作用来读出设备ID信息。测试中SPI传输/接收数据帧大小设定为1个字节(8bit)。由于DSPI模块传输接收均提供4级FIFO,测试中使用两种方式进行SPI数据发送,一种方式使用DMA通道发送读取设备ID查询命令和4次空写入数据,另一种方式通过执行代码(需要内核干预)发送读取设备ID查询命令和4次空写入数据。SPI数据接收均使用DMA完成。为了便于测试使用DMA模块是否降低内核负荷,在DSPI通信同时,主程序在While循环中不停翻转GPIO引脚(PTD7)。 SPI Flash AT26DF081A provides read device ID command(0x9f), will feedback 4 bytes device ID info(0x1F,0x45,0x01,0x00)。K60 works as SPI master send read ID command, then send 4 dummy write data to read back device ID info. During test, SPI data frame size setting to 1byte(8 bit). For DSPI module TX/RX FIFO is 4 entries, so there using two ways do SPI data transfer, one is using DMA CH1 send data, the other way using software code send data. SPI RX using DMA CH0 and in main while loop it will toggle PTD7 pin to show if using DMA module will reduce core work load. 测试流程图(方法一: 使用DMA CH1发送SPI数据): Test flow chart (Way1: Using DMA CH1 do SPI TX): 测试结果(Test Result): 执行一次读ID信息操作,需要花费12.96us,其中内核处理中断的时间为(2.56+2.72)= 5.28us。 根据客户要求,依照此方法每次发送3个字节,接收4个字节,SPI通信过程中内核负荷时间比率为 (5.28/16.16) =32.7% SPI read ID operation once, it will take 12.96us, includes core deal with interrupt time 5.28us. According to this way, customer want to TX 3bytes then RX 4bytes, during SPI communication core work load rate is 32.7% 测试流程图(方法二: 使用软件代码发送SPI数据): Test flow chart (Way2: Using software code do SPI TX): 测试结果(Test Result): 执行一次读ID信息操作,需要花费11.6us,其中内核处理中断的时间为(2.48+1.40)= 3.88us。 根据客户要求,依照此方法每次发送3个字节,接收4个字节,SPI通信过程中内核负荷时间比率为 (3.88/14.80) =26.2% SPI read ID operation once, it will take 11.6us, includes core deal with interrupt time 3.88us. According to this way, customer want to TX 3bytes then RX 4bytes, during SPI communication core work load rate is 26.2% 测试场景二:读取AT26DF081A设备9处不连续地址数据 Test scenario 2: Read 9 discontinue address data from AT26DF081A AT26DF081A设备提供读阵列命令(0x0B),可以连续读取多个字节数据。根据客户要求,测试读取9处不连续地址数据,每处读取4个字节。根据AT26DF081A设备要求,读阵列命令后需要再发送3个字节地址信息外加1个字节空写入数据,之后K60将会收到数据。即如果要读取4个字节数据,K60作为SPI主机需要发送9个字节数据(1个字节读阵列命令+3个字节地址+1个字节空写入+4个字节空写入)。测试中使用两个DMA通道进行SPI数据收发,两个DMA通道交替工作,DMA通道0(SPI接收)优先级高于DMA通道1(SPI发送)。完成9处数据采集后进入SPI中断,清除EOQ标志并且修正DMA通道配置,进行新的一轮9处数据读取测试。为了便于测试使用DMA模块是否降低内核负荷,在DSPI通信同时,主程序在While循环中不停翻转GPIO引脚(PTD7)。 SPI Flash AT26DF081A provides read array command (0x0B) to sequentially read a continuous stream of data out. With customer requirement, the test will read 9 discontinue address data, each address read 4 bytes data. AT26DF081A datasheet shows read array command with 3 bytes address and 1 dummy byte, then following will be data. In order to read 4 bytes data out, K60 as SPI master need TX 9 bytes data (1byte read array command + 3bytes address + 1byte dummy data + 4bytes dummy data). During the test, it using two DMA channels do SPI TX/RX, each channel alternatively work, DMA CH0(SPI RX) with higher priority than DMA CH1(SPI TX). When finish 9 discontinue address data receive, it will clear EOQ flag and refresh DMA CH0/1 setting in SPI interrupt for next round read 9 discontinue address data test. In main while loop it will toggle PTD7 pin to show if using DMA module will reduce core work load. 测试流程图(Test flow chart): 测试结果(Test Result): 读取AT26DF081A设备9处不连续地址数据,需要花费132.32us,其中内核处理中断的时间为2.6us。 根据客户要求,依照此方法每次发送3个字节,接收4个字节,重复9次。SPI通信过程中内核负荷时间比率为 (2.6/103.52) =2.5% SPI read ID operation once, it will take  132.32us , includes core deal with interrupt time 2.6us. According to this way, customer want to TX 3bytes then RX 4bytes, 9times,during SPI communication core work load rate is 2.5% DMA模块提供动态加载DMA传输控制描述符(TCD)功能,当需要连续多次执行SPI传输时,使用这种功能可以进一步减少内核负荷。 DMA module provides dynamic scatter/gather feature, which supports automatically loading a new TCD into a DMA channel. Using this feature will reduce core work load in SPI transfer continuously. 测试结果(使用DMA动态加载功能): Test Result(Using DMA dynamic scatter/gather feature ): 读取AT26DF081A设备9处不连续地址数据,需要花费130.68us,其中内核处理中断的时间为0.76us。 根据客户要求,依照此方法每次发送3个字节,接收4个字节,重复9次。SPI通信过程中内核负荷时间比率为 (0.76/101.88) =0.75% SPI read ID operation once, it will take 130.68 us , includes core deal with interrupt time 0.76us. According to this way, customer want to TX 3bytes then RX 4bytes, 9times,during SPI communication core work load rate is 0.75% 测试结论(Test conclusion) SPI通信过程中DMA模块使用方式不同对于减轻内核负荷作用差异明显。通常SPI进行大量数据传输接收,使用DMA模块能有效减少内核负荷。鉴于客户需求,使用测试场景二的方法可以有效降低内核负荷。 How to use DMA module to reduce core work load, different way lead to different result. In general, using DMA module do amounts of SPI data transfer will reduce core work load . According customer requirement, using test scenario 2 way reduce core work load dramatically。 为什么每次读操作之间需要SPI片选无效 (Why need deassert CS signal between each read operation)? 根据AT26DF081A手册要求,读ID命令和读阵列命令都需要使片选信号无效用以结束当前的读操作,换言之如果要开始新的读操作,需要结束之前的通信(使片选信号无效)。 AT26DF081A datasheet indicates deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. In order to start new read command operation, it need deassert the CS pin. 计算客户要求每次读命令间隔时间为SPI实际通信时间(以5MHz波特率发送7个字节重复9次 100.8us)加上内核处理中断时间。 According customer requirement SPI each read command interval time is SPI communication time (TX 7bytes 9times with 5MHz baud rate take 100.8us) add core deal with interrupt time. 测试代码(Test source code) 测试代码基于Kientis 100MHz Rev2例程中的[spi_demo]工程,将测试代码替换<spi_demo.c>和<isr.h>文件即可。 Test source code is based on KINETIS512_V2_SC (Kientis 100MHz Rev2 Example Project) [spi_demo] project, using test code instead of orignial <spi_demo.c>&<isr.h> files.
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  180°-Ansteuerung des BLDC-Motors simulation in LTSpice: Verläufe:           Es wurde als x-Koordinaten –Winkel in [°] statt der Zeit überzeichnet    
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To do: Implement a program that lets the 4 LEDs on the Tower walk like this: * a single LED from left to right, * then the two left ones, the two right ones, * the two outside and at least the two LEDs in the middle. For easy observing write a wait routine, called 'delay (unsigned int ms)', of about 1 second without using any library functions. The processor will start with the standard frequency of 20...25 MHz. Estimate the time, that a loop needs to realize the time. Hint: Do not forget to stop the Watchdog Module at the beginning. Result:TWR_K60_Lauflicht.zip  including a readme with the compiler options
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using the TAD tool
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With the HMI developing, touch sensing is more and more popular. The GPIO-based method was developed as a low-cost way to do touch sensing. NXP had developed this sensing method and provide as TSS library (which combines support for GPIO and hardware-based touch sensing).The GPIO method uses the RC charge time in a capacitor (the electrode or touch pad)   Measurement Principles: TSI Method TSI method uses configurable current sources. The current sources are active outputs, making them far more robust against noise. Current sources are configurable, making it possible to configure sampling time. The signal slope depends on the applied current and the capacitance. When a finger approaches the electrode, frequency decreases. Another oscillator, uses a internal unchanging capacitor, this is our reference, we will configure it to oscillate faster than the external one. By comparing how many reference oscillations where counted by the TSI module per external reference scan, we can know when a touch happened.
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       所谓“知识产权保护”,其实就是在产品量产之后防止其芯片内部代码通过外部调试器被有效读取出来的手段,毕竟现在来说硬件电路是比较容易被复制的,如果软件再不设防的话,在山寨技术如此发达的今天(用发达来形容貌似不是很过分吧,呵呵)这个产品估计很快就会被淘汰了。        因为最近有很多客户问到关于Kinetis的加密锁定问题,所以我觉着还是有必要对其细说说的。其实飞思卡尔对于知识产权保护方面还是做了很大的功夫的,而且使用起来也是比较方便的(这点很重要),具体可以参考Kinetis的Reference Manual中Security这一章,这里我就以在IAR环境下锁定K60为例介绍一下使用方法: 1. 首先简单介绍一下原理,即如果将K60置于Security状态(即锁定状态),则是不能通过Debug接口或者EzPort接口对芯片内部flash有任何操作的(CPU还是可以正常读写flash的,也就是说程序还是可以正常运行的,只不过是不能被外部非法读取了),当然“mass erase”命令除外(我们平时在Jlink Command窗口中敲入的unlock Kinetis命令就是触发这个命令给芯片的),通过“mass erase”命令可以再次将芯片擦除到出厂状态(即unsecure解锁的过程),这样芯片就又可以正常使用了(方便用户之后的程序升级)。咳咳,不过不用担心,解锁之后的芯片其内部的flash已经被完全擦除掉变为空片状态,也就是说内部的代码已经没有了,所以。。。懂的。。。呵呵; 2. 说完Security的原理,下面再聊聊K60实现security的process。我们可以通过K60的FTFL_FSEC寄存器中的SEC位来设定芯片的security状态,如下图所示,芯片默认出厂状态SEC位是为10的,即非加密锁定的,而如果将SEC位设定为00、01或者11任何一种情况,则芯片都将处于锁定状态(这就是我们接下来要干的事了,呵呵)。这里可能会有人疑问,在这个寄存器在重新上电之后会保存内容吗,我只能说“咳咳,都能抢答了”,哈哈,这正是我下面要说的; 3. K60在flash中0x00000400~0x0000040F这16个字节范围的地址定义为寄存器加载地址(Flash配置区),如下图所示,而这其中0x0000040C的地址内容在芯片上电之后会被自动加载到FTFT_FSEC寄存器中,也就是说我们只需要在烧写程序的时候把相应数据写到该flash地址即可在上电之后对芯片进行加密锁定,由此实现加密锁定。 4. 好了,原理和process都说完了,准备工作就做好了,下面就撸胳膊抹袖子开工干活吧,呵呵。其实飞思卡尔已经为我们做好了相关工作,只不过我们平时因为用不到没有注意到罢了。我们打开IAR环境,然后导入需要加密的代码工程,再打开工程目录下cpu文件组中的vectors.c和vectors.h(如果你的工程架构类似于飞思卡尔官方的sample code的话就在这个路径下)。在vectors.h里的最后部分我们会看到4个config段(共16个字节大小),如下图1,这四个段就是定义了上述0x400~0x40F的内容,其中CONFIG_4中最后的0xfe即为0x40C地址的内容(注意ARM处理器默认是little end模式的,所以0x40C在低地址),0xfe表明SEC位为10,即非加密状态,这样如果我把该0x40C地址的内容改成0xfc、0xfd或者0xff任意一个都可以实现对芯片的加密锁定。至于该四个配置段定义是如何映射到K60的flash区中的呢,去vectors.c文件中中断向量表vector_table[]的最后看看就知道了,如下图2; 5. 这里我们选择将CONFIG_4内容由原来的0xfffffffe改成0xfffffffd即可,然后保存编译通过之后,在查看其生成的s19文件中可以看到如下图所示,即0x40C地址的内容被修改成了0xfd,这样烧写文件就搞定了; 6. 当然到这一步实际上还没有完,其实在IAR的新版本之后(IAR6.6之后),其自带的flashloader默认是把0x400~0x40F这段保护起来的(防止误操作对芯片意外的security),即使如上面所述修改好相应内容,在烧写的过程中flashloader也不会对这段地址的内容做任何擦除和写入。为此还需要再额外对IAR的flashloader进行配置,具体步骤如下: (1)进入Options->Debugger->Download,选择如下: (2)点击“OK”,然后系统会提示保存该修改后的flashloader配置,建议把自己修改好的.board文件保存到自己的工程目录下,方便以后直接调用该flashloader。 7. 至此全部设置就搞定了,点击编译连接,然后下载,即可把加密后的代码烧写到芯片的flash里面去了。注意如果我们点击调试按钮的话,一旦程序烧进去之后调试器会自动复位芯片,此时加密状态位会被load到FTFT_FSEC[SEC]位中,芯片的调试端口就会被停掉,所以这时进入不到调试界面,而是弹出错误窗口,不用担心,因为此时程序已经正确烧到芯片中,我们重新插拔电源之后会看到程序已经正常执行,而此时的芯片已经处于加密状态。当然如果我们想再进入调试模式调试芯片的话,一种是通过Jlink Command窗口解锁,如下图1,另一种是再次点击调试按钮,会弹出解锁窗口,点击解锁即可,如下图2。 图1 图2
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