Kinetis Microcontrollers Knowledge Base

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Kinetis Microcontrollers Knowledge Base

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To do: Implement a program that lets the 4 LEDs on the Tower toggle all together using the PIT Interrupt. This time, let the program run in the Flash. * toggle period 0.5 s * extract vector table and service routines in 'vector.c' * Change the linker command file 'ldscript_flash' * Take care of the 16 Byte security settings from $400-$410 in the Flash. Do not overwrite!!! Hint: Use the 'arm_cm4.c and 'arm_cm4.h' from the freescale kinetis homepage, which include access functions for the NVIC. For ease of use, these routines are included in the result file. Result: TWR_K60_PIT0_Flash.zip
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The Kinetis family has abundant low power mode. Customers may confused to figure out the different way to wake up from the low power mode. 1)  In VLPR, VLPW:  the NVIC remains sensitive to interrupts, so any interrupt will be serviced. 2)  In Stop, VLPS:  the device can be waked up by USB wake up interrupt only. 3)  In LLS, VLLSx:  the device won't be able to wake up from any USB source. 4)  LLWU is used to wake up, so customer would able to wake up from any of the available LLWU wake up sources. As for the USB module, there has two different interrupts for a USB resume event. One asynchronous to be able to wake from a low power mode, which is triggered by change in the state of the USB lines. The other is synchronous and is triggered only after 2.5 us of detecting a K state (D+ = 0, D- = 1, for Full Speed). The application is responsible to transition to the low power mode whenever it requires it, and for this purpose it must check the device state as reported by the USB stack. When a suspend condition is detected in the bus, the SLEEP interrupt triggers and the stack changes its state to suspend; then the application will transition to the low power mode. When this SLEEP interrupt occurs, the asynchronous wake interrupt is enabled, and is disabled when it is triggered (this is required by the module to clear the interrupt). In normal conditions, the synchronous resume interrupt or the reset interrupt will be triggered afterwards, causing the stack to transition its state to other than suspend. The application can then know that communication is active again and will avoid entering the low power mode again.
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1. 使用J-Link+J-Flash给Kinesis烧写序列号(Program serial number for Kinetis by J-Link + J-Flash) 2. 教你用J-Flash ARM工具单独烧写程序到Kinetis 3. Cyclone Max 使用步骤及注意事项 4. 飞思卡尔常用脱机烧写工具 5. 离线烧写工具Cyclone Max使用方法及单次按键烧写两个image文件的实现方法​ 6.Kinetis 量产注意事项​
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Este proyecto se hizo teniendo en mente el consumo del agua en un hogar promedio para ayudar a no desperdiciarla; en un caso típico se tiene una cisterna a la que llega el agua directamente de la red de agua potable de la ciudad, también se cuenta con un tinaco y con una bomba de agua para trasladarla desde la cisterna. Tanto el tinaco como la cisterna cuentan con 2 sensores de nivel de agua, un nivel alto y un nivel bajo... Por dar un ejemplo, cuando la cisterna se encuentre totalmente llena y el tinaco vacío, la bomba encenderá para enviar agua al tinaco y continuará subiendo agua hasta que el sensor alto del tinaco detecte que ya está lleno y entonces se apagará la bomba; cuando el tinaco empiece a vaciarse y el nivel alto no detecte agua la bomba no encenderá, lo hará hasta que el nivel bajo del tinaco no detecte agua, de ésta manera se evita que la bomba esté prendiendo y apagando si es que se utiliza solo el sensor alto para encender y apagar la bomba. Un caso parecido será el de la cisterna; la cisterna solo enviará agua al tinaco si ésta se encuentra llena o si tiene un nivel medio de agua (por el hecho de estar mandando el líquido al tinaco) y en caso de estar vacía o aunque el nivel bajo esté detectando agua no prenderá la bomba hasta que el nivel alto detecte que ya está llena de nuevo, ésto para evitar (al igual que en el caso del tinaco) que con el simple cambio de un solo sensor esté prendiendo y apagando la bomba; es aquí donde se aplica la lógica y es el trabajo que hace en éste proyecto la tarjeta de freescale.
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Hello Freedom users I have created another full board review this time for the FRDM-KL05Z always including clear instructions to program and debug your first project. I'm still working on the video version (looking for a better accent :smileyconfused:), but the commands illustrated by screen captures should be easy to follow. Freescale Freedom development platform: [FRDM-K... | element14 Enjoy Greg
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Recently I was told that there really lack of enough document && demo regarding the lwIP stack with SDK. So I would like to share more detail regarding this topic, and hope it will been helpful and useful. Introduction Small independent implementations of the TCP/IP protocol suite One of the most widely used TCP/IP stack Under a BSD-style license Support run in both bare metal and RTOS environment Suitable for use in embedded system with tens of free RAM and room for around 40 kilobytes of code ROM lwIP stack on KSDK     - <ksdk_install_dir>/middleware/tcpip/lwip lwIP stack on KSDK - Code Structure lwIP code structure is shown as below: src     This subfolder includes the latest stable lwIP 1.4.1 source code which can be downloaded from this link: download.savannah.gnu.org/releases/lwip/ port     This subfolder includes the adapter code which adapts lwIP stack to SDK. lwIP stack on KSDK - Source Code Structure of source code under is shown below: lwIP stack on KSDK – Adapter code <ksdk_install_dir>/middleware/tcpip/lwip/port <ksdk_install_dir>/middleware/tcpip/lwip/port/arch These Adapter code could be divided into four types:         Ethernet driver adapter code         OSA adapter code         Additional code         lwIP stack configuration code Ethernet Driver Adapter Code Provide Ethernet relevant interface including    − Ethernet hardware initialization    − Network interface initialization    − Send packet to Ethernet hardware    − Receive packet from Ethernet hardware    − Pass packet to lwIP stack Both polling and interrupt mode are provided for packet receiving     - In <ksdk_install_dir>/platform/drivers/inc/fsl_enet_driver.h,          #define ENET_RECEIVE_ALL_INTERRUPT 0 to enable polling mode.          Or set          #define ENET_RECEIVE_ALL_INTERRUPT 1 to enable interrupt mode. Ethernet driver adapter code provides ENET_receive API for polling mode Under RTOS environment, a separate task executing ENET_receive for packet receiving is created in Ethernet hardware initialization code for polling mode Under Bare Metal environment the ENET_receive API need to be called endlessly to do packet receiving OSA Adapter Code Provide OS dependent types and interface for RTOS environment (configured NO_SYS = 0)    −Semaphore    −Mutex    −Mailbox    −Thread Provide time tick for bare metal environment(NO_SYS = 1) sys_now to get the current time sys_assert to print an assertion messages and abort execution. Additional Code Provide definition and interface for:    −Typedefs    −Compiler hints for packing and platform specific    −Diagnostic output lwIP Stack Configuration Code Provides a way to override much of the behavior of lwIP based on opt.h.     − Module support (Code size)           Default inclusions:     ARP (LWIP_ARP)     UDP (LWIP_UDP) and UDP-Lite (LWIP_UDPLITE)     TCP (LWIP_TCP) -- this is a big one!     Statistics (LWIP_STATS)          ……          Default exclusions:    DHCP (LWIP_DHCP)    AUTOIP (LWIP_AUTOIP)    SNMP (LWIP_SNMP)    IGMP (LWIP_IGMP)    PPP (PPP_SUPPORT)    − Memory management (RAM usage)              lwIP’s custom heap-based mem_malloc              C standard library malloc and free              Memory pools lwIP Stack Porting Guide    Possible Situation for Porting New Soc with Limited RAM In current KSDK, the main RAM consumption for lwIP is show below: If resource on the new platform is not enough, could reduce ram consumption for ram_heap and pbuf_pool.         In lwip/port/lwipopts.h: #define MEM_SIZE                (12*1024)    /**the size of ram_heap/ #define PBUF_POOL_SIZE          10      /*the number of buffers in the pbuf pool. */ #define PBUF_POOL_BUFSIZE       1518 /* the size of each pbuf in the pbuf pool. */ pbuf_pool also support dynamically allocate from ram_heap.        In lwip/include/opt.h:          #define MEMP_MEM_MALLOC     1 /*Use mem_malloc/mem_free to do allocate*/ Use libc malloc/free to manage the memory allocation instead of mem_malloc/mem_free, memory definition for ram_heap is not needed.         #define MEM_LIBC_MALLOC       1 /*Use malloc/free/realloc provided by C-library*/   New Soc NOT Support PIT timer OSA adapter code should provide Bare metal lwIP stack with a 1ms period timer. Current the code use pit timer to do this and the definition in sys_arch.c is as below: #define HWTIMER_LL_DEVIF    kPitDevif      // Use hardware timer PIT #define HWTIMER_LL_SRCCLK   kBusClock     // Source Clock for PIT #define HWTIMER_LL_ID       3 #define HWTIMER_PERIOD          1000      // 1 ms interval If the new platform does not provide PIT, we could use other hardware timers to implement the 1ms period timer. Lightweight TCP/IP (lwIP) Stack Porting v Lightweight TCP/IP (lwIP) Stack Porting Guide Lightweight TCP/IP (lwIP) Stack Porting Guide
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USB secondary ISP bootloader for LPC11U68  Overview        A Secondary Bootloader (SBL) is a piece of code that allows a user application code to be downloaded using alternative channels other than the standard UART0 used by the internal bootloader (on chip). Possible secondary bootloaders can be written for USB, Ethernet, SPI, SSP, CAN, and even I/Os. The secondary bootloader utilizes IAP as a method to update the user’s application code.        The internal bootloader is the firmware that resides in the microcontroller’s boot ROM block and is executed on power-up and resets. After the boot ROM’s execution, the secondary bootloader would be executed, which will then execute the user application.      The purpose of this document is to use USB as an example for developing the secondary bootloader and the code was tested using the LPCXpresso 11U68 evaluation board.       The MSCD presents easy integration with a PC‘s operating systems. This class allows the embedded system’s flash memory space be represented as a folder in Windows/Linux. The user can update the flash with the binary image using drag and drop, so the following sections will present a guideline for development and implementation of the USB secondary bootloader design, configuration, and test.      USB secondary bootloader code is base on the USB Mass Storage Class demo. However in this application note, we do not attempt to explain how the Mass Storage Class is implemented. Fig 1 LPCXpresso Board for LPC11U68 Setup file (sbl_config.h)       This file configures the secondary bootloader. The user should change this according to their application.       Some definitions and explanation: MAX_USER_SECTOR – This parameter is device dependent. In a 256 KB device, it will be 29 sectors, however the size of the last 5 sectors become the 32 KB instead of the 4 KB, so in the application, MAX_USER_SECTOR chooses 23 (Fig 2). CRP – Code Read Protection. This parameter allows select the desired CRP level. Choosing CRP3, the primary bootloader’s entry mechanism check will be bypassed. Fig 3 for CRP details. Fig 2 Flash sectors in LPC11U68 Fig 3 Code Read Protection (CRP) Secondary bootloader entry        The boot sequence shown below is used when entering the secondary USB bootloader. Fig 4 Using an entry pin      The secondary USB bootloader will check the status of a GPIO pin to determine if it should enter into programming mode. This is the easiest way since no post processing is needed. And this secondary bootloader uses P0.16. Automatic secondary bootloader entry       If the secondary USB bootloader detects that no user application is present upon reset, it will automatically enter programming mode. ISP entry disabled     If the secondary USB bootloader detects that a user application has already been installed and that CRP is set to level 3, then it will not enter ISP mode. Bootloader size        Since the bootloader resides within user programmable flash, it should be designed as small as possible. The larger the secondary USB bootloader is the less flash space is available to the user application. By default, the USB bootloader has been designed to fit within the first two flash sectors (Sector 0-1) so that the user application can start from sector 2. Code placement in flash       The secondary bootloader is placed at the starting address 0x0 so that it will be executed by the LPC11U68 after reset. Flash programming is based on a sector-by-sector basis. This means that the code for the user application should not be stored in any of the same flash sectors as the secondary bootloader and for efficient use of the flash space, the user application should be flashed into the next available empty sector after the bootloader.        In the application, the start sector is 3 (0x0000_3000) which is used to store the user application code. User application execution        If the SW2 button is not depressed, the secondary bootloader will start the execution of the user application. Execution of the user application is performed by updating the stack pointer (SP) and program counter (PC) registers. The SP points to the new location where the user application has allocated the top of its stack .The PC on the other hand contains the location of the first executable instruction in the user application. From here on the CPU will continue normal execution and initializations specified on the user application. By default, the bootloader uses 2 flash sectors. Therefore, to utilize the remaining flash, the secondary bootloader will look for the user application at 0x00003000 Handing interrupts      The LPC11U68 contains a NVIC (Nested Vectored Interrupt Controller) that handles all interrupts. When an interrupt occurs the processor uses the vector table to locate the address of the handler.      On the LPC11U68 the vector table is located in the same area of flash memory as the secondary bootloader. The secondary bootloader is designed to be permanently resident in flash memory and therefore it is not possible to update the contents of the vector table every time a new application is downloaded.       The Cortex-M3 core allows the vector table to be remapped; however this is not the case with the Cortex-M0. Because of this, the secondary bootloader has been designed to redirect the processor to the handler listed in a vector table located in the application area of flash memory, see Fig 5. Fig 5 User application       To execute the user application the secondary USB bootloader will load the new SP and PC values into their respective registers, allowing the CPU to execute the new code correctly. Therefore, the user application must be built so that it can run from that starting address. In the application, this address is 0x00003E00. So relocate the user application storage area by following corresponding IDE’s User Guide.  Testing  Creating the binary file             In this application, I build the demos_switch_blinky which is from the LPCOpen library to create the binary which is compatible with the secondary USB bootloader. The binary see Table 1. 08 04 00 10 B5 09 00 00 07 07 00 00 9B 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A1 E1 FF EF 00 00 00 00 00 00 00 00 00 00 00 00 A7 09 00 00 00 00 00 00 00 00 00 00 E5 09 00 00 27 03 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 01 03 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E3 09 00 00 E1 09 00 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 38 B5 63 4C 25 68 28 07 07 D5 96 20 E0 60 61 48 00 78 00 28 01 D1 00 F0 F7 F8 20 68 0C 21 29 40 01 43 21 60 31 BD 38 B5 5A 4C A0 78 40 1C A0 70 C0 B2 65 28 34 DB 00 25 A5 70 20 78 00 28 2F D0 60 78 00 28 03 D0 02 28 16 D0 0A D3 20 E0 01 21 00 F0 CA F8 00 21 01 20 00 F0 C6 F8 00 21 02 20 13 E0 01 21 01 20 00 F0 BF F8 00 21 00 20 00 F0 BB F8 00 21 02 20 08 E0 01 21 00 F0 B5 F8 00 21 01 20 00 F0 B1 F8 00 21 01 20 00 F0 AD F8 00 E0 65 70 60 78 40 1C 60 70 C0 B2 03 28 00 DB 65 70 31 BD F8 B5 00 F0 36 F9 00 F0 C2 F8 3A 48 01 68 02 22 91 43 01 60 01 68 38 4A 0A 40 02 60 35 4F 01 20 38 70 36 48 00 68 0A 21 00 F0 2B F9 1E 21 00 F0 28 F9 40 1E 00 26 80 21 49 04 88 42 0C D2 30 49 48 60 30 48 02 68 12 02 12 0A C0 23 1B 06 13 43 03 60 8E 60 07 20 08 60 01 20 2B 49 08 60 23 4C 20 00 00 F0 18 F9 29 48 01 68 80 22 12 03 0A 43 02 60 20 68 01 21 01 43 21 60 20 68 01 21 88 43 20 60 20 68 80 21 88 43 20 60 A6 60 FA 20 80 00 60 60 20 68 40 21 01 43 21 60 20 68 80 21 01 43 21 60 20 68 80 20 80 04 1A 49 08 60 20 68 30 21 01 43 21 60 18 4D 28 78 00 28 12 D1 38 78 00 28 0E D0 00 21 00 20 00 F0 3E F8 00 21 01 20 00 F0 3A F8 00 21 02 20 00 F0 36 F8 FA 20 80 00 E0 60 3E 70 E8 7B 00 28 E6 D1 01 20 38 70 E3 E7 00 40 02 40 04 00 00 10 00 20 00 A0 FF FF FE FF 00 00 00 10 10 E0 00 E0 20 ED 00 E0 1C 80 04 40 14 82 04 40 00 E1 00 E0 01 00 00 A0 49 01 40 18 83 54 70 47 10 B5 32 4C 20 00 00 F0 BF F8 E1 21 49 02 20 00 00 F0 C7 F8 03 20 E0 60 81 20 A0 60 80 20 20 63 10 BD 00 00 03 28 00 DB 70 47 80 B5 01 23 4B 40 2D A1 0A 5C 2B A1 09 5C A0 20 00 06 FF F7 DC FF 01 BD 00 00 03 28 00 DB 70 47 10 B5 A0 21 09 06 24 A2 12 5C 92 00 89 18 8C 22 92 01 01 23 00 BF 21 A4 20 5C 83 40 8B 50 10 BD 00 00 F8 B5 FF F7 C7 FF A0 25 2D 06 28 00 00 F0 B6 F8 00 24 00 BF 18 A6 31 5D 88 00 28 18 80 22 92 01 80 18 00 BF 15 A2 12 5D 03 68 01 27 97 40 1F 43 07 60 01 23 28 00 FF F7 A9 FF 64 1C 03 2C EA DB F1 BD 00 00 80 B5 07 48 01 68 80 22 52 02 0A 43 02 60 19 22 0A A1 04 48 00 F0 98 F8 01 BD 00 00 00 80 00 40 80 80 04 40 00 40 04 40 80 B5 FF F7 E9 FF 00 F0 B1 F8 01 BD 02 02 02 00 11 10 12 00 00 03 81 00 00 04 81 00 00 05 81 00 00 08 81 00 00 09 81 00 00 0B 02 00 00 0C 02 00 00 0D 02 00 00 0E 02 00 00 12 81 00 00 13 81 00 00 17 01 00 01 09 01 00 01 0B 81 00 01 0E 81 00 01 14 82 00 01 15 82 00 01 16 81 00 01 17 82 00 01 1A 81 00 01 1B 81 00 01 1D 81 00 02 00 01 00 02 01 01 00 02 03 82 00 80 B5 00 F0 EF F8 01 49 08 60 01 BD 00 00 00 10 80 B5 03 4A 12 68 12 69 52 68 90 47 02 BD 00 00 F8 1F FF 1F 03 48 01 68 80 22 D2 05 0A 43 02 60 70 47 00 00 80 80 04 40 15 49 01 22 8A 61 0A 68 80 23 5B 01 13 43 0B 60 07 21 81 60 10 21 81 62 70 47 70 B5 04 00 0D 00 01 20 0E 49 08 60 00 F0 8F F8 06 00 29 01 FF F7 D3 FF 01 00 E0 68 80 22 02 43 E2 60 C8 B2 20 60 08 04 00 0E 60 60 E0 68 80 22 90 43 E0 60 30 00 FF F7 C2 FF 70 BD 00 00 80 80 04 40 98 80 04 40 02 48 01 68 40 22 0A 43 02 60 70 47 80 80 04 40 00 2A 00 D1 70 47 30 B4 0C 68 23 0C 25 0A E4 B2 00 2C 12 D0 02 2C 01 D0 0A D3 11 E0 ED B2 AC 00 04 19 02 2D 01 DB F4 25 00 E0 F0 25 63 51 07 E0 2D 06 AC 0D 04 19 23 66 02 E0 2D 06 AC 0D 03 51 09 1D 52 1E E0 D1 30 BC 70 47 FE E7 38 B5 20 20 00 F0 E8 F8 00 20 00 90 11 48 02 E0 00 99 49 1C 00 91 00 99 81 42 F9 DB 01 20 00 F0 1F F8 0D 48 01 68 01 24 03 22 91 43 21 43 01 60 80 20 00 F0 C7 F8 09 4D 23 20 28 60 80 20 00 F0 CB F8 68 68 C0 07 FC D5 2C 67 03 20 00 F0 10 F8 31 BD 00 00 C4 09 00 00 10 C0 03 40 08 80 04 40 42 49 FF E7 08 60 00 20 48 60 01 20 48 60 70 47 3F 49 F7 E7 43 A0 CA 05 12 0F 92 00 80 58 C9 06 C9 0E 49 1C 49 00 FF F7 49 FF 00 BD 00 B5 00 20 3B 49 03 22 8B 6E 13 40 11 D0 02 2B 11 D0 02 D3 03 2B 10 D0 00 BD 89 6B 0A 40 08 D0 01 2A 03 D0 03 2A 1A D1 31 48 00 E0 2F 48 00 68 00 BD 2D 48 00 BD C9 69 D6 E7 8B 6B 1A 40 08 D0 01 2A 03 D0 03 2A 05 D1 29 48 00 E0 27 48 00 68 00 E0 25 48 09 68 C9 06 C9 0E 49 1C 48 43 00 BD 00 00 00 00 10 B5 00 20 22 4C 03 21 A2 6E 0A 40 30 D0 02 2A 15 D0 21 D3 03 2A 2C D1 A2 6B 11 40 08 D0 01 29 03 D0 03 29 05 D1 19 48 00 E0 17 48 00 68 00 E0 14 48 21 68 C9 06 C9 0E 49 1C 48 43 19 E0 E1 69 14 A0 CA 05 12 0F 92 00 80 58 C9 06 C9 0E 49 1C 49 00 FF F7 EB FE 0C E0 A2 6B 11 40 08 D0 01 29 03 D0 03 29 05 D1 09 48 00 E0 07 48 00 68 00 E0 04 48 21 6F FF F7 DA FE 10 BD 00 00 40 80 04 40 70 80 04 40 00 1B B7 00 D0 09 00 00 D4 09 00 00 08 80 04 40 00 00 00 00 C0 27 09 00 90 05 10 00 C0 5C 15 00 F0 B3 1A 00 20 0B 20 00 00 9F 24 00 E0 32 29 00 C0 C6 2D 00 50 97 31 00 E0 67 35 00 70 38 39 00 00 09 3D 00 40 16 40 00 80 23 43 00 C0 30 46 00 0B 49 0A 68 10 43 09 4A 02 40 C8 20 00 02 10 43 08 60 70 47 06 49 0A 68 82 43 04 48 10 40 C8 22 12 02 02 43 0A 60 70 47 00 00 00 00 FF 25 00 00 38 82 04 40 70 B4 01 21 00 22 13 E0 04 68 00 1D 0C 42 02 D0 4D 46 6D 1E 64 19 22 60 24 1D 1B 1F 04 2B FA D2 25 00 9E 07 01 D5 22 80 AD 1C 0B 40 00 D0 2A 70 03 68 00 1D 00 2B E7 D1 70 BC 70 47 10 B5 07 49 79 44 18 31 06 4C 7C 44 16 34 04 E0 08 1D 0A 68 89 18 88 47 01 00 A1 42 F8 D1 10 BD 08 00 00 00 14 00 00 00 9D FF FF FF 08 00 00 00 00 00 00 10 00 00 00 00 00 F0 0B F8 00 28 01 D0 FF F7 DE FF 00 20 00 BF 00 BF FF F7 0C FD 00 F0 02 F8 01 20 70 47 80 B5 00 F0 02 F8 01 BD FE E7 07 46 38 46 00 F0 02 F8 FB E7 FE E7 20 21 09 03 26 31 18 20 AB BE F9 E7 01 48 80 47 01 48 00 47 D9 09 00 00 C5 09 00 00 00 BF 00 BF 00 BF 00 BF FF F7 D2 FF 00 1B B7 00 00 80 00 00 80 B5 FF F7 DF FD 01 BD FE E7 FE E7 FE E7                                                    Table 1 Drag and drop the binary file Running the secondary bootloader, and connect a USB cable between the PC and the J3, see Fig 6; Fig 6 Drag and drop the binary file to the driver, see Fig 7;    Fig 7 Review the values of the user application in the relative area , see Fig 8; Fig 8
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The Multipurpose Clock Generator module explained by Ali Piña, Freescale TIC. MCG Module Explanation Connection Diagram Operation Modes Hands On Toggle a LED in FEI (FLL engaged Internal) switch to PEE (PLL Engaged External). Watch changes. Switch from different operation modes. El Módulo de MCG (Multipurpose Clock Generator) presentado por Ali Piña, Freescale TIC. Explicación del Modulo MCG. Diagrama de conexiones Modos de operación. Hands-On Togglear un LED en modo FEI (FLL engaged Internal) y cambiar a PEE(PLL Engaged External). Observar cambios. Moverse entre varios modos de operación
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KL17 reference manual V4.1 and V5.1 with updated Figure 13-2. Kinetis Bootloader Start-up Flowchart at page 179 There with modification to add "is direct boot valid" check. Please check below picture for the detailed info: The "is direct boot valid" check function is not supported for KL17 product, the correct flow chart should be below: The "is direct boot valid" check function is reserved for further parts(such as KL82), which has one bit in BCA filed to control running code in QSPI Flash or internal Flash: Thank you for the attention.
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1. 飞思卡尔常用调试工具 2. 使用OpenSDA平台作为J-Link调试Kinetis 3. 使用OpenSDA平台作为USBDM调试Kinetis 4. 使用MTB模块快速跟踪定位Cortex-M0+指令执行状态(Use MTB in Cortex-M0+ to trace instructions) 5. KL25被加密,芯片锁死问题? 6. 对比几款流行的Kinetis调试器速度 7. 修复Jlink固件损坏的方法 8. Jlink调试Kinetis L系列的使用方法 9. CMSIS-DAP调试器在IAR v7.1中问题(Probe not Found)修复 10. FRDM_KL26 虚拟串口安装失败的解决方法 11. 使用J-Link TCP-IP Server通过以太网远程下载程序到Kinetis 12.Kinetis LOCK的原因及解决方案​
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Gracias a la excelente respuesta por parte de los concursantes, les informamos que daremos a conocer los proyectos finalistas el próximo martes 26 de Noviembre de 2013, a través de la comunidad Freescale y redes sociales; recibimos proyectos con gran potencial que aún están siendo evaluados por nuestros jueces. A continuación te compartimos los criterios a evaluar: • Alineación con las tendencias del futuro (Salud y Seguridad, Efecto Net,Going Green) • Creatividad • Innovación • Utilidad de la aplicación • Beneficio ambiental potencial para el uso del producto. Los finalistas seleccionados tendrán la oportunidad de presentar su prototipo en el evento Freescale Cup 2013 el día 7 de Diciembre de 2013 en el Tecnológico de Monterrey, Campus Guadalajara; donde el proyecto ganador será elegido por los asistentes al evento, a través de la comunidad Freescale y redes sociales. Recuerda que el ganador viajará con todos los gastos pagados al Freescale Technology Forum (FTF) en Dallas, Texas. Mantente atento el próximo martes 26 de Noviembre de 2013 y descubre los proyectos finalistas, tú puedes ser uno de ellos.
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This demo is about driving TFT LCD by FlexBus module on MAPS-K22 board.       MAPS-K22 brief description: High performance Freescale ARM Cortex™ M4 SoC MK22FN512VLL12​ with 120MHz core clock, 512KB Flash and 128K RAM. Support Graphic LCD by Flexbus interface. Power supply from Micro USB 5V. Support ISO7816 smart card by UART interface. Support connector for Peripheral, Application and Socket MAPS board. SDK 1.0 Software release FlexBus Overview       The FlexBus module is a hardware module that: Provides memory expansion and provides connection to external peripherals with a parallel bus Can be directly connected to the following asynchronous or synchronous slave-only devices with little or no additional circuitry: External ROMs Flash memories Programmable logic devices Other simple target (slave) devices Block diagram Pin functions Pins allocation Demo illustration       After run the demo, the TFT LCD will display the Freescale logo as below, and I’ve also attached the demo. Welcome to download it.
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Hi, all The default AN2295 UART bootloader doesn't work well on K21/other Kinetis because of using FEI and complicated autocalibration mechanism. I made a simple version to make it works on MK21DX128VMC5, FYI. Readm.txt: UART bootloader for K21. (Default is MK21DX128VMC5) 128KB_Pflash_64KB_Dflash.icf is application link script example for MK21DX128 used together with UART bootloader, UART bootloader use 0x0 - 0xFFF. Q: Why need this patch? A: The original AN2295 use internal RC and FLL output as system clock. The calibration mechanism is not stable. The main change of this patch is to use external cystal plus PLL as system clock to communicate with PC software. Changes to AN2295 1) Add MK21D5.h for K21 support 2) Add AN2295_TWR_K21_cfg.h for K21 support(Copy from AN2295_TWR_K60_cfg.h) 3) AN2295_TWR_K21_cfg.h    1> #define KINETIS_MODEL K21_50MHz    2> #define KINETIS_FLASH FLASH_128K    3> #define BOOT_UART_BASE UART2_BASE_PTR       #define BOOT_UART_GPIO_PORT PORTE_BASE_PTR       #define BOOT_UART_GPIO_PIN_RX   17       #define BOOT_UART_GPIO_PIN_TX   16    4> #define BOOT_PIN_ENABLE_NUM        7 4) Add mcg folder and mcg.c/mcg.h 5) kinetis_params.h:    1> Modify SRS_REG/SRS_POR_MASK/INIT_CLOCKS_TO_MODULES to meet MK21D5.h    2> Add PORT_PCR_PS_MASK for BOOTLOADER_PIN_ENABLE_INIT to enable Pull-up. 6) bootloader.h: #define BOOT_WAITING_TIMEOUT 500. PC software can't communicate to bootloader if only 1s delay. 7) bootloader.c:    1> #include "mcg.h"    2> Use 25MHz PEE:       SIM_CLKDIV1 = ( 0    | SIM_CLKDIV1_OUTDIV1(1)                            | SIM_CLKDIV1_OUTDIV2(1)                            | SIM_CLKDIV1_OUTDIV4(1));             (void)pll_init(8000000,       /* CLKIN0 frequency */                      LOW_POWER,     /* Set the oscillator for low power mode */                      CRYSTAL,       /* Crystal or canned oscillator clock input */                      4,             /* PLL predivider value */                      25,            /* PLL multiplier */                      MCGOUT);       /* Use the output from this PLL as the MCGOUT */    3> Restore to FEI mode before jump to Application:       pee_pbe(8000000);       pbe_fbe(8000000);       fbe_fei(32768); Knowing issues: 1) Don't use virtualCOM from OSJTAG, it's very hard to communicate with PC software. Use RS232 in TWR-SER2. 2) BOOTLOADER_CRC_ENABLE must be 0, otherwise PC software will report unknown protocol version
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Test Environment: FRDM-KL43Z Rev. A MCUXpresso IDE v10.2.0 MCUXpresso SDK for FRDM-KL43Z V2.4.1(2018-06-18) Create new project in MCUXpresso IDE select [New project...], there will pop the SDK Wizard panel, then select [frdmkl43z]: Then, click [Next] will enter into [Configure the project] panel, we can set the [Project name] and select [flexio_i2s] in [driver]: Click [Finish], the new project was created. In general, the project is based on [hello_world] project with board default console available. In [Project Explorer], we could find the <fsl_flexio_i2s.c> & <fsl_flexio_i2s.h> & <fsl_flexio.c> & <fsl_flexio.h> files in drivers folder: Edit the code The application note AN5397 detailed introduce how FlexIO emulate I2S bus communication. The MCUXpresso SDK <flexio_i2s> driver using the AN5397 showed second solution to use two timers and two shifters. Please check here to get more detailed info. The I2S signal was below, we need to use four FlexIO pins to provide: BCLK, Fss, TxData & RxData. In <pin_mux.c> file, it need to config pin function, we use PTD7 pin provide I2S BCLK clock; PTD6 pin as I2S Frame_sync pin; PTD5 pin as Tx data pin; PTD6 pin as Rx data pin; In <frdmkl43z_flexio_i2s_interrupt_tx.c>,  config flexio_i2s and config the audio frame format: Please check attached source code for the detailed project info. Test result From the actual measured I2S signal, it shows the 8 bytes was sent out:
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Download Kinetis M bare-metal drivers and software examples installation file. Changes in 4.1.6 : Modified FreeRTOS kernel to disable all interrupts prior entry to critical section and enable all interrupts upon exiting from critical section. This kernel behavior is compatible with standard FreeRTOS port to the ARM Cortex-M0 core. All freertos_cfg header files updated to reflect kernel change. Updated PLL_Disable macro and Quad Timer driver. Added UART_SetBaudRate macro. Removed RCM_ClrResetFlags macro. Fixed issue of generating callback events after conversion for these ADC channels with interrupt disabled.
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Installation file containing training examples - unpack and run this file to install code examples.
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Hi, Anybody has sample code for K22 SPI? where shall I get the same? Thank Sarvani
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1 Abstract      LIN (Local Interconnect Network) is a concept for low cost automotive networks, which complements the existing portfolio of automotive multiplex networks. LIN is based on the UART/SCT protocol. It can be used in the area of automotive, home appliance, office equipment, etc. The UART module in NXP kinetis L series contains the LIN slave function, it can be used as the LIN slave device in the LIN bus. Because there is few LIN slave KL sample code for the customer’s reference in our website, now this document mainly take KL43 as an example, explain how to use the FRDM-KL43 board as the LIN slave node to communicate with the LIN master device. LIN master use the specific LIN module: PCAN-USB Pro FD. Master send the publisher ID and subscriber ID, slave give the according LIN data response. This document will share the according code, hardware connection and the test result. 2 LIN bus basic knowledge review         For the convenient to understand the LIN bus, this chapter simply describe the basic knowledge for LIN bus. Mainly about the LIN topology and the LIN frame. 2.1 LIN bus topology structure       LIN bus just use the simple low cost single-wire, it uses single master to communicate with multiple slaves. The bus voltage is 12V, the speed can up to 20 kbit/s. LIN network can connect 16 nodes, but in the practical usage, normally use below 12 nodes. Figure 2-1. LIN bus topology 2.2 LIN bus frame structure          LIN Frame consists of a header (provided by the master task) and a response (provided by a slave task).     Master send publisher frame: Master send header+ data +checksum; slave just receive.     Master send subscriber frame: Master send header; slave receive send data +checksum.     The following figure is the structure of a LIN frame: Figure 2-2. LIN frame structure      LIN frame is constructed of one Break field, sync byte field (0X55), PID, data and checksum. 2.2.1 Break filed and break delimiter Break filed is consist of break and break delimiter. Break should at least 13 nominal bit times of dominant value (low voltage). The break delimiter shall be at least one nominal bit time long (high voltage). Figure 2-3. break field 2.2.2 Sync byte field Sync is a byte field with the data value 0X55. The byte field is the standard UART protocol. Figure 2-4. The sync byte field 2.2.3 Protected identifier field A protected identifier field consists of two sub-fields: the frame identifier and the parity. Bits 0 to 5 are the frame identifier and bits 6 and 7 are the parity.     ID value range: 0x00-0x3f, 64 IDs in total. It determine the frame categories and direction. Figure 2-5. The sync byte field P0 = ID0 xor ID1 xor ID2 xor ID4 P1 = -(ID1 xor ID3 xor ID4 xor ID5) -is NOT。  ID can be split in three categories:   Frame categories Frame ID Signal carrying frame Unconditional frame 0x00-0x3B Event triggered frame Sporadic frame Diagnostic frame Master request frame 0x3c Slave response frame 0x3d Reserved frame   0x3e,0x3f     2.2.4 DATA       A frame carries between one and eight bytes of data. The number of data contained in a frame with a specific frame identifier shall be agreed by the publisher and all subscribers.      For data entities longer than one byte, the entity LSB is contained in the byte sent first and the entity MSB in the byte sent last (little-endian). The data fields are labeled data 1, data 2,... up to maximum data 8. 2.2.5 checksum  The checksum contains the inverted eight bits sum with carry over all data bytes or all data bytes and the protected identifier.        Classic checksum: Checksum calculation over the data bytes. Enhanced checksum: Checksum calculation over the data bytes and the protected identifier byte.  Method: eight bits sum with carry is equivalent to sum all values and subtract 255 every time the sum is greater or equal to 256, at last, the sum data do bitwise invert.  In the receive side, do the same sum, but at last, don’t do invert, then add the received checksum data, if the result is 0XFF, it is correct, otherwise, it is wrong. 3 KL43 LIN slave example    This chapter use KL43 as the LIN slave, and communicate with the specific LIN master device, realize the LIN data sending and receiving. 3.1 Hardware prepare Hardware: FRDM-KL43,TRK-KEA8,PCAN-USB Pro FD       LIN bus voltage is 12V, but the FRDM-KL43 don’t have the LIN transceiver, so we need the external LIN transceiver connect the KL43 uart, to realize the LIN voltage switch. Here we use the TRK-KEA8 on board LIN transceiver MC33662LEF for the KL43. The MC33662LEF circuit is like this:    Figure 3-1. LIN transceiver schematic 3.1.1 FRDM-KL43 and TRK-KEA8 connections      FRDM-KL43 need to connect the UART port to the LIN transceiver. The connection shows in this table: No. FRDM-KL43 TRK-KEA8 note 1 J1-2 J10-5 UART0_RX 2 J1-4 J10-6 UART0_TX 3 J3-14 J14-1 GND 3.1.2 TRK-KEA8 and LIN master connections         LIN bus is using the signal wire.  TRK-KEA8 J14_4 is the LIN wire, it should connect with the LIN wire in PCAN-USB Pro FD. GND also need to connect together.        TRK-KEA8 P1 need a 12V DC supplier. Master also need 12V DC supplier. 3.1.3 Object connection picture   Figure 3-2. Object connections 3.2 Software flow chart and code      Now describe how to realize the LIN master and the LIN slave data transfer. LIN master send a publisher frame, the slave will receive the according data. LIN master send a subscriber frame, the slave will send the data to the master. The code is based on the KSDK2.2_FRDM-KL43 lpuart, add the LIN operation code.  3.2.1 Software flow chart         Figure 3-3. Software flow chart   3.2.2 software code     Code is based on KSDK2.2_FRDM-KL43 lpuart project, add the LIN operation code, the added code is list as follows: void LPUART0_IRQHandler(void) {      if(LPUART0->STAT & LPUART_STAT_LBKDIF_MASK)      {        LPUART0->STAT |= LPUART_STAT_LBKDIF_MASK;// clear the bit        Lin_BKflag = 1;        cnt = 0;        state = RECV_SYN;        DisableLinBreak;          }     if(LPUART0->STAT & LPUART_STAT_RDRF_MASK)      {                  rxbuff[cnt] = (uint8_t)((LPUART0->DATA) & 0xff);                  switch(state)          {             case RECV_SYN:                           if(0x55 == rxbuff[cnt])                           {                               state = RECV_PID;                           }                           else                           {                               state = IDLE;                               DisableLinBreak;                           }                           break;             case RECV_PID:                           if(0xAD == rxbuff[cnt])                           {                               state = RECV_DATA;                           }                           else if(0XEC == rxbuff[cnt])                           {                               state = SEND_DATA;                           }                           else                           {                               state = IDLE;                               DisableLinBreak;                           }                           break;             case RECV_DATA:                           recdatacnt++;                           if(recdatacnt >= 4) // 3 Bytes data + 1 Bytes checksum                           {                               recdatacnt=0;                               state = RECV_SYN;                               EnableLinBreak;                           }                           break;          default:break;                                    }                  cnt++;      }     } void uart_LIN_break(void) {     LPUART0->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);   //Disable UART0 first     LPUART0->STAT |= LPUART_STAT_BRK13_MASK; //13 bit times LPUART0->STAT |= LPUART_STAT_LBKDE_MASK;//LIN break detection enable LPUART0->BAUD |= LPUART_BAUD_LBKDIE_MASK;         LPUART0->CTRL |= (LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);     LPUART0->CTRL |= LPUART_CTRL_RIE_MASK;     EnableIRQ(LPUART0_IRQn);    } int main(void) {     uint8_t ch;     lpuart_config_t config;     BOARD_InitPins();     BOARD_BootClockRUN();     CLOCK_SetLpuart0Clock(0x1U);     LPUART_GetDefaultConfig(&config);     config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;     config.enableTx = true;     config.enableRx = true;     LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ);     uart_LIN_break();     while (1)     {        if(state == SEND_DATA)        {           while((LPUART0->STAT & LPUART_STAT_TDRE_MASK) == 0); // hex mode                   LPUART0->DATA = 0X01;           while((LPUART0->STAT & LPUART_STAT_TDRE_MASK) == 0); // hex mode                   LPUART0->DATA = 0X02;           while((LPUART0->STAT & LPUART_STAT_TDRE_MASK) == 0); // hex mode                   LPUART0->DATA = 0X10;//Checksum   0X10 correct, 0xaa is wrong           recdatacnt=0;           state = RECV_SYN;           EnableLinBreak;        }     } }     4 KL43 LIN slave test result   Master defines two frames: Unconditional ID Protected ID Direction Data checksum 0X2C 0XEC subscriber 0x01,0x02 0x10 0X2D 0XAD Publisher 0x01,0x02,0x03 0x4c    Now, master send 0X2C and 0X2D data, give the test result and the according waveform. 4.1 LIN master configuration Uart baud rate is: 9600bps 4.2  Send ID 0X2C and 0X2D frame       From the PC software of LIN master, we can find 0X2D ID can send the data successfully, and 0X2C ID can receive the correct data (0x01, 0x02) and checksum (0x10) from the KL43 LIN slave side. 4.2.1 0X2D ID frame oscilloscope waveform and debug result      From the debug result, we can find the buff can receive the correct ID, data and checksum from the LIN master.    4.2.2 0X2C ID frame oscilloscope waveform 4.2.3 0X2C ID SLAVE send back the wrong checksum     From the PC software, we can find if the KL43 code modify the checksum to the wrong data 0XAA, then the PC software will display the checksum error. This is the according oscilloscope waveform for the wrong checksum data. From all the above test result. We can find, KL43 as the LIN slave, it can receive the correct data from the LIN master, and when LIN master send the subscriber ID, kl43 also can send back the correct LIN data to the master. More detail, please check the attached code project. BTW, LIN spec can be downloaded from this link: http://www.cs-group.de/wp-content/uploads/2016/11/LIN_Specification_Package_2.2A.pdf   Attached is the code and the pdf version of this document:                  
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