Engineering clock for FRDM-KE02Z40M

[Circuit_Man]

Hi NXP Community,

I have the FRDM-KE02Z40M board that has a 10MHz crystal. What is the engineering clock frequency for this uC? Usually this is derived from the crystal's frequency, for other MCU boards that I have worked with. I need this frequency for my timing subroutines, like a 20ms timing subroutine.

Thanks

[diego_charles]

Hi Circuit Man,

I think that you are making reference to the Core clock frequency.

According the KE02 RM chapter 20 internal clock source, the internal clock is selected, since FLL Engaged Internal mode is automatically selected out of reset. Using MCUXpresso Config tools (Clocks Tool) and after selecting this FLL mode I have obtained 32 MHz of core clock frequency.

If  you are using the MCUxpresso SDK, after running the BOARD_InitBootClocks();  the MCU is running with  internal clock mode in FEE mode , core clock is 40 MHz.

However, I recommend you use the fsl_clock API, to determine any clock frequency from several IP's, including the Clock frequency.

uint32_t CLOCK_GetFreq(clock_name_t clockName);

This can be an easier way to determine clock values, for your delay API.

Additionally , If you  are interested in Config tools, You can check our trainning videos and documentation, this tools helps users to initialize peripherals and clocks using a graphic interface.

https://www.nxp.com/design/training/basic-application-development-using-mcuxpresso-ide-and-mcuxpress...

And as a final recommendation, you can check out PIT timer demo in the KE02 SDK , for example,  you can use the PIT timer to gererate delays. Our PIT API uses the clock frequency to calculate timings.

I hope this helps,
Diego.

[Circuit_Man]

Hi Diego,

Thank you for your response. I appreciate your help. But I have a question about your answer below. If the crystal's frequency is 10MHz, how can the KE02 core clock run at 40MHz? Doesn't the crystal set the maximum frequency of operation for the uC?

Thanks.

[diego_charles]

Hi @Circuit_Man 

Thank you for your reply!

The internal FLL (frequency lock loop) generates a 40 MHz Core clock frequency by multiplying a reference clock by 1024, that way we are able to operate the MCU at a higher frequency than the one generated by the 10 MHz oscilator.

There are lots of documentation on the web detailing the operation of FLL´s and PLL´s. To complement my reply a bit more, besides the information in the RM  you could look at the following application notes:

AN4757Migration Guide Chatpter 6 Clock modules from S08 to Kinetis E Family Clock modules.

 If you like, you can also look at this application note  https://www.nxp.com/docs/en/application-note/AN3041.pdf#page=3 where the FLL operation for the oldschool HCS08 MCU is described briefly.

I hope this could help you!

Yours,

Diego