i.MX8 MSCALE SERIES DDR Tool Release (V2.10)

Document created by Oliver Chen Employee on Jan 26, 2018Last modified by m_j on May 16, 2019
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       i.MX8MSCALE DDR Tool is a Windows based software to help users to do LPDDR4/DDR4/DDR3L training, stress test and DDR initial code generation for u-boot SPL. Because this tool need to access Windows registry, users must run it in administrator mode. When users design a new MX8M board, please make sure to follow the rules, which can help users to esaily bring up DDR devices on the i.MX 8MSCALE board.

  1. Reserve i.MX 8M serial download mode, i.MX 8M UART1 and USB1 slave mode, which are used by i.MX 8M DDR Tool.
  2. Use the same PMIC and DDR power supply connection as i.MX 8M EVK board, or guarantee DDR power supply is no need to adjust when it boots to serial download mode.

 

If you have any questions or report bugs, please help to create ticket in the community.

 

Note: please read user guide inside the package carefully before you use this tool.

 

Sample configuration in the front of the .ds script for i.MX8M debug UART2:

################step 0: configure debug uart port. Assumes use of UART IO Pads.   #####

##### If using non-UART pads (i.e. using other pads to mux out the UART signals), #####

##### then it is up to the user to overwrite the following IO register settings   #####

memory set

0x3033023C

32

0x00000000

#IOMUXC_SW_MUX_UART2_RXD

memory set

0x30330240

32

0x00000000

#IOMUXC_SW_MUX_UART2_TXD

memory set

0x303304A4

32

0x0000000E

#IOMUXC_SW_PAD_UART2_RXD

memory set

0x303304A8

32

0x0000000E

#IOMUXC_SW_PAD_UART2_TXD

memory set

0x303304FC

32

0x00000000

#IOMUXC_SW_MUX_UART2_SEL_RXD

sysparam set

debug_uart

1

#UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)

 

Sample configuration in the front of the .ds script for i.MX8M debug UART3 

################step 0: configure debug uart port. Assumes use of UART IO Pads.   #####

##### If using non-UART pads (i.e. using other pads to mux out the UART signals), #####

##### then it is up to the user to overwrite the following IO register settings   #####

memory set

0x30330244

32

0x00000000

#IOMUXC_SW_MUX_UART3_RXD

memory set

0x30330248

32

0x00000000

#IOMUXC_SW_MUX_UART3_TXD

memory set

0x303304AC

32

0x0000000E

#IOMUXC_SW_PAD_UART3_RXD

memory set

0x303304B0

32

0x0000000E

#IOMUXC_SW_PAD_UART3_TXD

memory set

0x30330504

32

0x00000002

#IOMUXC_SW_MUX_UART3_SEL_RXD

sysparam set

debug_uart

2

#UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)

 

====================================================================================================================================

Feature list for v2.10 release:

  • Change DDR4 capacity computing method

====================================================================================================================================

Feature list for v2.00 release:

  • Add support to i.MX8M-mini

====================================================================================================================================

Feature list for v1.1.2 release:

  • Add support to change default debug UART to other UART ports

====================================================================================================================================

Feature list for v1.1.1 release:

  • Modify DDR frequency point from 668 to 667 in generated ARRAY code if you choose 1600MHz/334MHz DDR script to align with BSP code.

====================================================================================================================================

Feature list for v1.1 release:

  • Change tool name to mscale_ddr_tool to support future mscale series CPU
  • Add 'ARRAY' format of generated code to align with the latest version of NXP uboot-imx DDR driver
  • Reserve 'CODE' format of generated code for old version of uboot-imx and study purpose.
  • Update DDR scripts based on the latest RPA tool.

====================================================================================================================================

Feature list for v1.0 release:

  • Use the latest scripts generated from register_programming_aid tool
  •  Fix minor GUI issues
  • If you have suspend/resume or DVFS issues when you applies generated LPDDR4 SPL code, please replace the original bl31.bin with the attached one when making u-boot image.
  • If you want to build your own bl31.bin, please apply 0001-ATF-support-to-different-LPDDR4-configurations.patch

====================================================================================================================================

Feature list for beta release:

  • Support LPDDR4/DDR4/DDR3L 16/32bit mode
  • Support LPDDR4/DDR4 up to 4 frequency points
  • Support LPDDR4/DDR4 1D+2D training
  • Support code generation for i.MX 8M u-boot SPL DDR initial code

====================================================================================================================================

 

MX8MM Register Programming Aid (RPA) DRAM PLL setting

The RPAs provide a default DRAM PLL setting (DRAM frequency) based on the default setting supported in u-boot.  It is highly recommended to use the default DRAM frequency settings in the RPA for ease of use and to align with u-boot.  Otherwise, in addition to updating the RPA for the new DRAM frequency, the u-boot SPL code itself will need to be manually updated with the new DRAM PLL setting.

 

Should the user wish to change the DRAM frequency, the following steps are required:

 

[1] First, the user needs to update the RPA Register Configuration worksheet tab

Device Information table “Clock Cycle Freq (MHz)“ setting to the desired DRAM frequency

 

 

[2] Next, in the RPA DDR stress test file worksheet tab search for “memory set 0x30360054”.  The address “0x30360054” is the register address for the DRAM PLL and its setting needs to be updated to the desired frequency. 

 

 

Note that there is another place where the DRAM frequency is also updated “freq0 set 0x30360054” but it is automatically updated based on the setting above. 

 

Below is a table of various frequencies to choose from.  For frequencies not listed in the table below, it is up to the user to calculate a new register setting based on the formula:  (24MHz x m)/(p x 2^s)

 

Where “m” represents the PLL_MAIN_DIV, “p” represents the PLL_PRE_DIV, and “s” represents the PLL_POST_DIV.  Note that the DRAM frequency is double the DRAM PLL frequency:  DRAM_freq = DRAM_PLL x 2

 

The DRAM PLL register and bit settings are shown below:

 

 

  

The following table provides examples of the various settings to create the desired frequency:

 

 

For example, in the MX8MM LPDDR4 RPA where the default DRAM frequency is 1500MHz, let’s assume that the user instead wants 1200MHz. 

First, the user changes the RPA Register Configuration worksheet tab Device Information table “Clock Cycle Freq (MHz)“ setting to 1200.

Next, in the RPA DDR stress test file worksheet tab search for “memory set 0x30360054” and replace “0xFA080” (original setting from DRAM frequency 1500MHz) with “0x0012C032” (updated for DRAM frequency 1200MHz).  Note that for a DRAM frequency of 1200MHz, the DRAM PLL is configured for 600MHz, as the DRAM frequency is double the DRAM_PLL.

 

The steps outlined above are sufficient in order to create a DDR script for use with the DDR stress test tool to run calibration and execute the DDR stress test.  However, to deploy the generated code in SPL, more steps are needed as the u-boot SPL DDR driver does not automatically change the DRAM PLL according to the generated code. Hence the user will need to manually modify related code in u-boot.  It is highly recommended to work with a software engineer familiar with u-boot when making the following modifications. 

 

[3] Modify DRAM PLL configuration in uboot-imx/drivers/ddr/imx8m.c, specifically the code highlighted below (function call dram_pll_init).  Note that the files and file paths in u-boot change frequently, so if this particular file (or file path) does not exist in the current u-boot, simply search for dram_pll_init or ddr_init.

 

void ddr_init(struct dram_timing_info *dram_timing)

{

……

   debug("DDRINFO: cfg clk\n");

     if (is_imx8mq())

          dram_pll_init(DRAM_PLL_OUT_800M);

     else

         dram_pll_init(DRAM_PLL_OUT_750M);

……

 }

 

In the above code, the user should update the macro “DRAM_PLL_OUT_750M” with the new DRAM PLL value.  Note that the default DRAM_PLL_OUT_750M results in the a DRAM frequency of 1500MHz, where the DRAM frequency is double the DRAM PLL (as previously stated above).

 

For example, if the user desires to run the DRAM at 1200MHz, they would change the above to:

dram_pll_init(DRAM_PLL_OUT_600M);

 

Note that DRAM_PLL_OUT_600M is a supported macro in the dram_pll_init() API.  If the desired DRAM PLL configuration does not exist in dram_pll_init(), you will need to add support in

uboot-imx/arch/arm/mach-imx/imx8m.c (as stated above, if this file path does not exist in the current u-boot simply search for dram_pll_init):

 

void dram_pll_init(enum dram_pll_out_val pll_val)

{

……

}

 

 

 

Related resource link:

i.MX 6 DDR Stress Test old Tool-v1.03

i.MX 6/7 DDR Stress test GUI Tool

i.MX 8M Application Processor Related Resource

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