I am working on a design where I need the KL02 input ESD protection to clamp the input signal. I can limit the input signal current using a resistor, but the voltage may be up to +/-25 V. I have read the datasheet (KL02P32M48SF0 rev4 08/2014) and saw page 7 which said:
All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/| IICIO| .
But this only discusses negative voltage and current, not positive. In addition, the above states there is no diode connection to VDD, so presumably there is a different ESD structure to limit positive ESD events. Is it adequate to limit the positive current to the same value of | Iicio | = 3 mA?