KL02 Min Max Input Current Voltage

[marky]

I am working on a design where I need the KL02 input ESD protection to clamp the input signal.  I can limit the input signal current using a resistor, but the voltage may be up to +/-25 V.  I have read the datasheet (KL02P32M48SF0 rev4 08/2014) and saw page 7 which said:

All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/| IICIO| .

But this only discusses negative voltage and current, not positive.  In addition, the above states there is no diode connection to VDD, so presumably there is a different ESD structure to limit positive ESD events.  Is it adequate to limit the positive current to the same value of | Iicio | = 3 mA?

[john_suchyta · Accepted solution]

Hi Marky,

The KL02 GPIO does not allow positive current injection due to the absence of the diode to VDD. There is a diode to an internal floating bus, but it cannot be used to limit external voltage as you propose. Here are comments regarding several of the items that appear in the discussions below.

The basic info for the KL02 (not K series or KL04) is that the maximum input voltage is related to VDD (VDD+0.3V) AND is limited to a max value (3.8V).

The reason for 3.8V is that it is a technology limit, which also affects reliability.

The reason for 0.3V offsets for negative and positive input levels is that this is below the protection diode forward voltage (around 0.6V) so that the diodes don’t conduct significant current into or out of their respective rails. In the negative level case there is a diode to VSS so that negative voltage transitions get clamped to VSS.

On the positive overvoltage side, there is a diode from each pin (I/O and VDD, but not true open-drain) to an internal ESD bus. While we won’t see diode conduction with positive overvoltages, they are driving the internal ESD bus to that higher voltage. Therefore, we have to set a max limit for the positive voltage – VDD+0.3V.

Current injection is only allowed on pins that have diodes to the rails. Note that this is a DC spec, for slow changing signals like high voltage AC measurement. Since all KL02 pins have diodes to VSS, negative current injection is allowed on all GPIO pins. Since none of the KL02 GPIO pins have diodes to VDD, positive current injection is not allowed – an external diode is required. Injected current must be limited to prevent disruption to the internal supply rails.

Bottom lines:

An input voltage of 4.1V violates the spec at any VDD level.

The max VDD level for normal operation is 3.6V.

The absolute maximum VDD level is 3.8V, but it does not mean that all specifications will be guaranteed.

The max input level is VDD+0.3V. If VDD is 3.6V, engineering judgment should be used for any signals that will exceed 3.8V.

The KL02 does not allow positive current injection since there is no diode to VDD. An external diode to VDD is required. A current limiting resistor is required to ensure the diode forward voltage does not exceed the max pin input voltage.

Regards,

John Suchyta

[marky]

General advice is great for people that need it, but I was hoping for specifics.  The IO pins obviously have circuitry to deal with positive transients like ESD.  This circuitry must do some clamping and must be able to absorb some energy.  Unfortunately, NXP does not provide any useful information in utilizing this circuitry in a a safe and reliable manner.  "Don't use it" is of course safe and reliable but adds potentially unnecessary cost and board space to a design.  In the interests of the community I provide some quick measurements on a KL02Z32 on pin PTA11 with the part powered and the pin connected to a variable voltage supply with a 1 MOhm current limiting resistor.  All following values are approximate and just one part, room temp, etc etc.  The pin's voltage was 5.2V at 1uA input current, 6.1V at 10uA, and 6.4V at 20 uA.  I suspect the input structure is similar or identical to 5V tolerant parts.  However, this part is not specified for 5V inputs, perhaps because that would require additional cost for production testing, perhaps because process controls would need to be tighter or yields would be lower, or perhaps other reasons.  Again, utilizing this circuitry could be useful in some designs, but doing so is at the user's risk with no promises or even design information available from NXP.

[egoodii]

Despite your measurements, with 'no available information to the contrary' I suppose you will have to take the 'safe option' and limit, with hardware, such pins to < (Vdd+0.3V).

[marky]

With my current design, an input pin is exposed to occasional transients of tens of volts with no current limit but with transient energy limited to less than the energy discharged in the 5kV HBM ESD testing stated in the datasheet (5kV, 100pF 1/2 C V^2).  Of several prototype units, I had one unit where the KL02 uC input pin went low impedance (~2.3 kOhm) to Vdd but still functioned.  I knew I was using the part beyond its typical use, so that one event prompted me to try to get more information on the device -- this discussion.  Not sure how much the discussion helped, because I will do what I was already planning on doing -- adding a current-limiting resistor.  Part of the reason for a resistor vs. a voltage clamping device is board space and layout.  Thanks for your input though.  Because of you there was more interesting discussion with Hui_Ma at NXP.  Interesting that at least two pins (if not more) on KL02 are 5V tolerant but not stated as such on the datasheet.  I could see 5V tolerant inputs being useful in some designs.

[egoodii]

Thank you for those actual measurements!  They further underscore a requirement for NXP to clarify the voltage-tolerance on 'presumably' that set of pins NOT analog-capable, or RESET or Crystal, and then fix this (and MOST KL datasheets!) relative to these requirements!  KL02 and KL03 datasheets seem to have the limitations we have discussed here -- KL04 does show minus AND PLUS clamp currents, BUT Iicio in Table 5 for 'positive injection current' shows +current for Vin < Vss-0.3, as copied from 'negative injection' -- a minor typo....  The KL05 Table-1 numbers make sense, although 'note 1' only mentions dual-clamp-diodes relative to analog pins -- I should expect it applies to ALL I/O pins?

[marky]

Thanks Earl, you addressed my question though it is not the answer I was hoping for.  The IO pin input voltage (VIO) is rated -0.3 to VDD + 0.3 V.  And yet the ESD rating is +/-500 and +/-2000 V.  There must be an on-chip structure for +V ESD events that performs some clamping and can absorb some energy.  But doing what you say and limiting the input voltage to VDD + 0.3 V using additional components is certainly safe and reasonable.  Finding the board space is the hard part.

[egoodii]

I have to agree that the statements 'No diode to Vdd' and 'max Vdd+0.3" are incongruous.  On parts that specifically tout 5V-tolerance on I/O (looking at K60-100 for instance) the Vih(max) is given as 5.5V, independent from Vdd (on pins with such tolerance, does not apply to all digital I/O).  And for such part the injection current is given only as -5mA for such pins, but also listed is +/-5mA for clamped pins (analog-capable, reset, crystal) -- plus the 'regional limits'.  I think NXP will have to clarify the KL I/O structures for you!!!!

[Hui_Ma]

Hi

I would recommend customer to refer below thread about input injection current:

To Kinetis product, the DC injection current is +/-5mA.

https://community.nxp.com/thread/433880

Wish it helps.

Have a great day,
Ma Hui
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[marky]

Do all Kinetis product have the same DC injection current?  Although KL03 datasheet states 5 mA, I am using KL02.  KL02 datasheet (KL02P32M48SF0 rev4 08/2014) states 3 mA.  Note that these are negative voltages and currents, whereas my questions is about positive voltages and currents.  Perhaps the other referenced thread about input injection current helps, but I could not find the referenced thread.  The above link loops back to this thread.

[Hui_Ma]

Hi

Sorry for previous incorrect link address, correct link is :

https://community.nxp.com/thread/432843 

There is no diode tie to VDD, which direct tie to the internal ESD bus.

The pad input voltage should not exceed the KL02 datasheet showed 3.6V.

The negative DC inject current is -3mA is clamped VSS ESD protection diode spec requirement.

Obviously, there is no DC inject current data for clamped VDD ESD protection diode.

My previous mentioned Kinetis product DC injection current is for Kinetis K family product.

Sorry for bring the confusion.

Wish it helps.

Have a great day,
Ma Hui
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[egoodii]

Sorry, but that is exactly the point here -- the KL02 datasheet DOESN'T say Vin(max) 3.6V, it says Vdd+0.3 (Table 4 of section 1.4, Vio Min./Max.), and Vdd absolute-max 3.8V.  The 'Vdd +0.3V' requirement doesn't make any SENSE if there IS no explicit or implicit diode-clamp to Vdd on the digital-only I/O pins.  I would expect such pins to specifically list a fixed Vin(max) based on breakdown, as did the K60-100.  If that is indeed 3.6V, then so be it -- but isn't 3.8V+0.3V=4.1V?

[Hui_Ma]

Hi

The KL02 datasheet table 4 voltage and current operation ratings VIO value is the IO pin could tolerance ultimate max. voltage up to 4.1V. While, this value is instantaneous Max. tolerance input voltage value, not the long-term normally working Max. input voltage value. Customer need to refer Table 5 for voltage operating requirements for long-term working IO pin input voltage need below Max. value 3.6V.

Wish it helps.

Have a great day,
Ma Hui
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[egoodii]

I don't know what datasheet YOU are looking at -- the newest KL02 I can find on the NXP web is dated 8/2014 (Rev 4, KL02P20M48SF0.pdf.  Same date/rev/info for KL02P32M48SF0.pdf), and for those two years these datasheets have shown these errors and omissions.  Table 5 does NOT give ANY positive voltage limit information on Vin, ONLY on Vdd, AND Vin threshold-information based on Vdd ranges.  The 4.1V I posited 'from Table 4' is a simple calculation of the two voltage parameters there, but is based on the VERY FLAWED PREMISE that the IO pin voltage is limited by a Vdd +0.3 clamp, which actual measurements have PROVEN to be INCORRECT --- note 1 of Table 5 IS correct in that there IS no direct clamp to Vdd.  And I AGREE that any inference from Table 4 is an 'absolute max', NOT an 'operating level'.

Ideally NXP would fix the datasheets and release new revisions, for (at least!) ALL the KL0x devices, to clear up the errors, omissions, and ambiguous information regarding the input structure specifications for max Vih --- or at LEAST release datasheet errata.

[Hui_Ma]

Hi all,

We are checking the same datasheet.

Yes, I do agree with you about the KL product datasheet issue. There should with more explicit data about related IO pin input voltage. The datasheet should show more detailed info, not just bring confusion.

I will pass related voice to the Kinetis L product team.

Thank you for the input, I really appreciate that feedback.

Thank you for the attention.

with regards,

Hui

[marky]

Thank you for the support.  Personally, I would not describe the datasheets as incorrect, but rather overly conservative and not as complete as we would like.  General comments as a first time user of a Kinetis uC:

1. Table 4 is labeled "Voltage and current operating ratings".  Most companies call this something like "Absolute Maximum Ratings".  After all, Table 4 says the supply voltage can be -0.3 to 3.8 V, but the part will definitely not be operational powered at -0.3 V.  Some companies put a note for this table regarding the part is not necessarily operational (functional), won't be damaged by short-term exposure to these levels, but may be damaged by long-term exposure.
2. Table 4's VIO input pin voltage minimum of -0.3 V shouldn't be taken literally since Table 5 indicates this can be exceeded (more negative than -0.3 V) if the current is limited.  Of course the whole point of this discussion topic is to have similar information for exceeding the positive limit in Table 4.
3. Table 3 has ESD ratings.  This table indicates the part will not be damaged by transient voltages that are orders of magnitude higher than the voltages in Table 4.  My interest for my design is regarding non-ESD transients.  Without getting further information from NXP, I may look at the test conditions in the ESD standards, calculate the amount of discharge energy, safety factor the energy down by a factor of 3 to 10, then use that value to choose a current-limiting resistor for positive transients.  Ideally, manufacturers would provide max currents, voltages and/or energies with durations from DC to nanoseconds.  Some passive component manufacturers do this (resistors for example).  This would be useful information for the customer using the part, but the time/effort on the supplier's side is significant.

I am asking what maximum positive current or energy can safely be applied to an IO pin without causing damage and/or without causing a functional issue.  The part's ESD structure clearly can handle some level of current and energy, and I would like to take advantage of it.  Since the NXP answer so far is basically "don't utilize the part's ESD structure" by limiting the positive voltage to VDD+0.3V, I consider my question still unanswered.

[Hui_Ma]

Hi

Thank you for the patience.

For the KL02 product standard I/O pin(normal drive pad), the Max. positive current is 5mA;

The High drive pad, the Max. positive current is 20mA.

Wish it helps.

Have a great day,
Ma Hui
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[egoodii]

Nice information -- but what does DRIVE CURRENT have to do with input-voltage-withstand in 'input mode'????

[Hui_Ma]

Hi

The KL02 chip includes four pins, PTB0, PTB1, PTA12, and PTA13, with high current drive capability. These pins can be used to drive LED or power MOSFET directly. So, those four pins could tolerance input current up to 20mA.

The KL02 chip includes two pins, PTB3 and PTB4, with true open drain setting. These pins have the capability to support 5 V voltage input in 3.3 V systems. Those pins could tolerance input current Max. value is 5mA.

The other IO pins are normal drive pin, which input current Max. value is 5mA.

In general, after reset, the digital IO pins go to a disabled (high impedance) state. So if the input voltage doesn't exceed the operation range (Max. 3.6V), there doesn't generate damage current.

The pins with analog functionality will default to their analog functions. If the input voltage doesn't exceed the operation range (Max. 3.6V), the analog pin could not be damaged.

The previous mentioned input current is available, when the related pin configured as GPIO input function.

Wish it helps.

Have a great day,
Ma Hui
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[egoodii]

Ignoring the information about drive-power-level, as in 'high impedance' state that is certainly completely irrelevant.  I would like to know where you get a SPEC for 5V-tolerance on PTB3 and PTB4, and where you get the 3.6V-max rating for all other digital input pins!  Given the voltage-input measurements Marky made, I assure you there is NO WAY to 'shove' 5 or 20mA INTO an input-mode pin!

[Hui_Ma]

Hi

Related GPIO info could be found at page 75 chapter 3.10.1.1 of KL02 reference manual.

Wish it helps.

Have a great day,
Ma Hui
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