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Vybrid DDR3 write leveling

Question asked by Thomas Fredriksen on Jun 29, 2016
Latest reply on Sep 20, 2016 by Yuri Muhin

We are currently working on write leveling, gate training and read leveling on a Vybrid-based board with external DDR3 memory (Micron MT41K256M16HA-125 AIT:E). Unfortunately, we are unable to obtain any values for the rising edge using the procedures described in chapter 10.1.16 of the Vybrid Reference Manual (rev. 8).

 

First of all; it is not clear about the order of these procedures. Assuming that the manual list the procedures in the correct order, we have focused on getting the rising edge in write-leveling first.

 

It seems that, using table 10-25 (page 1593), we keep adjusting WRLVL_DL_X for data slices 0 and 1 until they reach zero. At this point, we terminate the leveling procedure, using 0x00 for the write leveling delay. The board boots with with this value, but it also boots without any leveling/training at all.

 

Any help would be greatly appreciated.

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