Hello NXP team,
Our customer is using Vybrid with DDR3 and they have questions about DDR leveling in Vrybrid RM.
Could you answer the following questions?
Case 1) In case of fly-by topology.
I think that read/write leveling and gate training is meaningful only for fly-by topology.
In case of Vybrid, fly-by topology can be applied to 8-bit width DDR memory x 2 pcs.
(Please correct me if this understanding is wrong)
In VFxxx Controller Reference Manual, Rev. 8, 11/2015 , 10.1.6.16.3.1 Software Gate Training in MC Evaluation Mode, we can find the following description.
3. Add a ½ clock cycle increment to the DQS gate by setting
PHY02[GATE_CFG] and PHY18[GATE_CFG] = 1.
But register description says that SW_HALF_CYCLE_SHIFT is only used for Write level training.
Is this typo? I think it should be "EN_HALF_CAS" in this context because it is used for Gate training.
Question 2) As for read leveling, Table 10-27 is not referred from any description in this RM.
How we can translate this table? We need to understand relationship between SWLVL_RESP_x in CR94/CR95 and this table.
Question 3) The edge we should set for the read leveling is rising edge of DQS? We should do the read leveling on both falling and rising edge?
Question 4) Our software should set the adjusted values in SWLVL_RESP_X to RDLVLD_DL_X?
Question 5) Do you have any reference code for DDR read/write leveling and gate training which followed the leveling operation in RM?
Case 2) In case of non fly-by topology.
In case single DDR3 memory is connected to Vybrid (16 bit width x 1 pcs), read/write leveling is not needed in our understanding. But we think that still DQS training (or DQS calibration) is useful to get optimum timing of DDR signals correct? I think that registers to control these timings can be the same registers that are used for leveling such as RDLVL_DL. But software processing for non fly-by topology differs from read/write leveling.
For this purpose, "VYBRID DDR VALIDATION TOOL" is useful to get optimum number for DDRMC registers?