LPSPI Peripheral Chip Select

[Angel487]

Hello NXP Community

On my project I need to drive a decoder/demultiplexer with SPI "chip select" pins (Pcs0, Pcs1, Pcs2).

This pins must be all active high (done) and I also need to drive more than one pin high or low.

This last requirement doesn't seem to be provided by the "fsl_lpspi" NXP driver.

I also tried to drive the pins as normal GPIOs, but this results in an out of timing behavior of CS.

Can you please help me?!

Thanks in Advance! 

Angelo

P.S. we are using this logic with de decoder since we have more than 4 chips on the SPI bus (see the attached schematics)

[kerryzhou · Accepted solution]

Hi @Angel487 ，

   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

  I checked the LPSPI IP module, from the register, just can select one PCS pin:

TCR register:

If you want more than one pin as the SPI_CS function.

Just the LPSPI IP hardware, no register to select it.

So, maybe still need to use the GPIO method.

You mentioned:

I also tried to drive the pins as normal GPIOs, but this results in an out of timing behavior of CS.

What's the detail situation? Which timing behavior is out?

Can you share some wave about it?

If you think the normal GPIO speed is slow, you can use the fast GPIO:

https://www.cnblogs.com/henjay724/p/15518705.html

If just the CS area is not correct, it is related to your GPIO CS code insert area, you need to go to the fsl_lpspi to add it.

With it helps you!

Best Regards,

Kerry