iMX6UL - DDR ADDR drive strength read-only

[nickbedbury]

For the iMX6UL, why is the drive strength (DSE) setting for DDR ADDRn pins in IOMUX read-only?

For example, see the IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 section of the reference manual:

I would have expected the DSE bitfield to have a variety of configurable options, since ADDR is an output of the iMX6...  But instead DSE is disabled and read-only.

[igorpadykov · Accepted solution]

Hi Nick

these settings are configured by SW_PAD_CTL_GRP_ADDDS SW GRP Register
(IOMUXC_SW_PAD_CTL_GRP_ADDDS), described in sect.30.5.288 i.MX6UL

Reference Manual.

Best regards
igor
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[nickbedbury]

Thanks, I was not aware of that register