We want to set i.MX6ULL output 800x600-60 VESA timing.
We use 4.1.15_1.1.0 BSP version
My device tree display timing is
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <40000000>;
hactive = <800>;
vactive = <600>;
hback-porch = <88>;
hfront-porch = <40>;
vback-porch = <23>;
vfront-porch = <1>;
hsync-len = <128>;
vsync-len = <4>;
de-active = <1>;
hsync-active = <1>;
vsync-active = <1>;
pixelclk-active = <0>;
};
};
};
and lcdif_sel is select pll5
I also check clock tree information.
pll5_bypass_src 1 1 24000000 0 0
pll5 1 1 649515096 0 0
pll5_bypass 1 1 649515096 0 0
pll5_video 1 1 649515096 0 0
pll5_post_div 1 1 324757548 0 0
pll5_video_div 1 1 324757548 0 0
lcdif_pre_sel 1 1 324757548 0 0
lcdif_pred 1 1 108252516 0 0
lcdif_podf 1 1 36084172 0 0
lcdif_pix 1 1 36084172 0 0
iomuxc 0 0 36084172 0 0
lcdif_sel 0 0 36084172 0 0
And We also check waveform from scope , clock is 36.27M
How to let lcdif_sel out 40MHz ?
Hi Appolo
one can try to set pll5 (which is currently = 649515096) to other frequency
so it could be divided to produce 40MHz. One can printf ccm registers
following Figure 18-2. Clock Tree i.MX6ULL RM
http://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf
Also may be useful try to change clock sources using example on
IMX6Q Device Tree Binding for ADV7343 Encoder
Best regards
igor
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Hi Sir,
As I understand ,i.MX6Q/D/DL/SOLO can reference device tree "clock-frequency" to output currect pixel clock if we use pll5.
Does mxsfb.c don't reference "clock-frequency" ?
OR
If I need to setting VESA timing *640x480-60 ,800x600-60" , I need to add PLL5=fixed clock into C file ?