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IMX6Q Device Tree Binding for ADV7343 Encoder

Question asked by Anuradha Ranasinghe on Sep 19, 2016
Latest reply on Feb 8, 2017 by Anuradha Ranasinghe

Hello all,

 

We intend to use ADV7343 video encoder with IMX6Q (specifically IMX6Q Sabrelite) parallel RGB interface (DISP_DAT). I need to figure out few things on device tree binding and how to adapt it to this encoder. I am using BD Linux Kernel : boundary-imx_3.14.52_1.1.0_ga and the corresponding dts file has the notations of for adv7180 device :-

 

pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */
>;
};

pinctrl_i2c3_adv7180_gpios: i2c3-adv7180_gpiosgrp {

fsl,pins = <
/* No data enable pin, make sure it is not selected */
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b1
#define GP_ADV7180_PWN <&gpio3 13 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0
#define GP_ADV7180_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0
#define GPIRQ_ADV7180 <&gpio5 0 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
>;
};

 

Can some one explain why we have two such nodes for this chip ? Has anyone done this for adv7343 chip ? 

 

Thanks

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