i.MX6/Enet: CRC/FCS errors

[bastian_schick]

Hi

I am noticed that I get FCS error while sending if TDAR is written even if it is set (100 out of 100,000 packets).

But this seems not to be the known erratum for the ENET.

I am using a i.MX6Q on a Phytec phyFlex-i.MX6Q board running non-linux, sending and receiving every 40us a packet.

I know there is a bandwidth limit (measured 600MB/s) but the FCS errors come even at a bandwidth of 200MB/s.

Did anyone experience the same?

[bastian_schick · Accepted solution]

For reference: The problem wasn't TDAR or the errata, but a wrong IOMUX setup for the DDR-RAM: CMOS instead to differential on some pins. This resulted in a bit error from time to time.