ddr3 data lines swapped + imx6sl

[jagsgediya]

Hi,

We are developing a custom board based on the imx6sl evolution kit. We are going to use 2 ddr3 through single chip select. both ddr are 256 MB size.

Now for better routing purpose, We have swapped the ddr data lines coming from the processor.

data byte 1 from processor is connected to dql0 to dql7 on 1st ddr. but this line are swapped for efficient routing like, d6 from processor is connected to dql0 of ddr etc.

data byte 2 from processor id connected to 2nd ddr's dql0 to dql7. similarly data byte3 from processor connected to dqu0 to dqu7.

We have also swapped the dqs lines between different bytes. like dqs0 is for byte1, dqs2 is for byte2, dqs1 is for byte3 etc.

So,  for dqs and data lines swapping what changes we need to do in ddr controller registers?

Is this approach fine?

Thanks,

Jags

[Yuri]

1.

   According to section 2.5.1 (Swapping data lines) of the "Hardware Development Guidefor i.MX 6SoloLite" :

The rules are as follows:

• Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane

by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)

— D0, D8, D16, D24, D32, D40, D48, and D56 are fixed

— Other data lines free to swap within byte lane

• JEDEC DDR3 memory restrictions are:

– No restrictions for complete byte lane swapping

– DQS and DQM must follow lanes.

2.

No need for specific memory controller settings.

3.

Please let us look at the connection scheme (i.MX6-SL <-> DDR3) for assurance.

Have a great day,
Yuri

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[jagsgediya]

Hi Yuri,

Thanks for the informative reply.

Below is the pic. of my ddr3 connection with imx6sl.

Please suggest the hardware and software changes.

[eduardocorreia]

Dear Jags,

Sorry for the totally off-topic message, but we are design a custom board too and we are going to implement a ethernet switch based on Marvell 88E6060 and I would like to talk to you since I saw in previous posts that you already used it and probably have a verified design. Would it be OK for us to have some e-mails about it? ercorreia@gmail.com

Best regards and Thank you!

[Yuri]

Hi, Jags Gediya !

The only point :

for Write Leveling it is recommended D0, D8, D16, D24 to be fixed.
Please consult with DDR3 Datasheet if memory requires using just the LSB
in Write Leveling, the DDR3 device can use all byte during Write Leveling.

Have a great day,

Yuri

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