VPU Decoding core clock setting in i.MX515

[ko-hey]

Hi all

I plan to use VPU of i.MX515.

So I read MCIMX51RM Rev. 1 2/2010 but I can't find how to set a decoding core clock domain (cclk).

I know the decoding core clock comes from the CCM module because I found the following description in section 61.2.1.

All VPU input clock and reset sources come from the i.MX51 CCM module. The VPU does not do clock gating internally.

However, I can't understand which register do I set.

Q1.

Could you specify which register do I set to use VPU ?

Q2.

According to the section 61.4.2 of RM, the decoding core clock domain's frequency can scale done through the VPU API.

I can't find the API in L2.6.35_10.11.01_ER_docs/doc/mx5/i.MX5x_Linux_VPU_API.pdf.

Which VPU API can set the core clock frequency ?

Ko-hey

[ko-hey]

Could someone follow and answer the following question ?

I checked MCIMX51RM Rev. 1 2/2010 onemore time and found the CCGR5 Register can enable the VPU clock.

CG3 field can enable "vpu clocks" and CG4 field can enable "vpu reference clock".

On the other hand, according to the Figure 7-41 and Figure 7-44 of RM, the clock relate to VPU is as follow.

VPU_AXI_CLK_ROOT

VPU_RCLK_ROOT

Q1-1.

VPU_AXI_CLK_ROOT will be enable when user set CG3 field to "11".

Am I correct ?

Q1-2.

VPU_RCLK_ROOT will be enable when user set CG4 field to "11".

Am I correct ?

Q2 

According to the section 61.4.2 of RM, the decoding core clock domain's frequency can scale done through the VPU API.

I can't find the API in L2.6.35_10.11.01_ER_docs/doc/mx5/i.MX5x_Linux_VPU_API.pdf.

Which VPU API can set the core clock frequency ?

Ko-hey

[art · Accepted solution]

Q. VPU_AXI_CLK_ROOT will be enable when user set CG3 field to "11". Am I correct ?

A. Yes.

Q. VPU_RCLK_ROOT will be enable when user set CG4 field to "11". Am I correct ?

A. Yes.

Q. Which VPU API can set the core clock frequency ?

A. Actually, there is some inaccuracy in the manual. In fact, the decoding clock is derived from the AXI clock and has the equal frequency (typically, 166MHz). There is no separate mechanism to change the decoding clock frequency.

Have a great day,
Artur

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[ko-hey]

So would you revise the manual ?

Ko-hey

[art]

Actually, i.MX51 is quite obsolete part, so, I don't think that someone will ever revise its documentation.

Artur

[ko-hey]

Okay, thanks.

Ko-hey