Question about delay step of MMDC Read and Write calibration

[ko-hey]

Hi all,

I have question about delay step of MMDC Read and Write calibration.

Could someone answer for the delay step ?

The following description is in the MMDCx_MPRDDLCTL of reference manual.

(RD_DL_ABS_OFFSET0 / 256) * MMDC_CH0 AXI clock (fast clock).

So for the default value of 64 we get a quarter cycle delay.

I understand that the AXI Clock (fast clock) is recognized as 1/2 of SDRAM Clock.

(264 MHz when the SDRAM Clock is 528 MHz)

Q1.

AXI Clock (fast clock) is 1/2 of SDRAM Clock.

Is the above understanding correct?

Q2.

Is it actually 1/256 unit of SDRAM Clock?

It's easy to understand that a quarter cycle is the default that takes the middle of data that changes in half a cycle (DDR).

However, if it is 4/1 of the AXI clock, it will be 1/2 of the DDR clock, and the default value and the adjustment range are too large.

In addition, the calibration log by the test tool is actually 1 → 0 → 1 The changing 0 (OK) range is also equivalent to an average of 76 steps in the OFFSET value, which translates into an impossible result exceeding 1124 ps and a half cycle (947 ps) of the SDRAM clock.

Ko-hey

[Yuri]

Hello,

  According to the following Community Q&A: Delay units in SDCLKx_DEL of MMDCx_MPSDCTRL register 

"The delay elements in the SDCLK path are similar to those in the data strobes but they are not exactly the same.

The delay is on the order of picoseconds, though, not a full SDCLK cycle as might have been interpreted from

the older document."

Have a great day,
Yuri

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