Q&A: Delay units in SDCLKx_DEL of MMDCx_MPSDCTRL register

Document created by grantw on Sep 5, 2013
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Question:

Clarify if the delay units, mentioned in  i.MX6 RM in two places are the same :
1. There are delay units for data strobes, that are considered in calibration procedures.
2. There are delay units for clocks SDCLK, mentioned in section 44.12.54 “MMDC PHY CK Control Register (MMDCx_MPSDCTRL)” of the RM.

 

General delay units description states :
“ The delay issued by the delay-line (according to the configured value) is absolute and takes into account the operating and temperature conditions. The delay-line has a resolution that may vary from device to device; an increment of 1 delay unit may vary between 20 pSec to 50 pSec.”

 

It may be guessed that the same relates to SDCLK delays, but preliminary i.MX6 specs mention that bit fields SDCLKx_DEL (x=0,1) control SDCLK delay, that can be up to 1 cycle.  This means SDCLKx_DEL step is 1/4  of the SDCLK.

 

Please clarify SDCLK delays (SDCLKx_DEL) in more details.


Answer:
"The delay elements in the SDCLK path are similar to those in the data strobes but they are not exactly the same.

The delay is on the order of picoseconds, though, not a full SDCLK cycle as might have been interpreted from the older document."

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