Hi!
For an external chip I would need a 27MHz clock signal which I'd like to create using PLL4 within the I.MX6UL. Currently I'm in an evaluation stage so I'm using the devmem command within busybox to write and read registers.
So far I started successfully PLL4 with the appropriate registers. At least PLL4's lock-bit can be read as locked, as the MSB of the 32 bits is high:
# devmem 0x20C8070 32
0x8000201F
Next step would be to output the clock on pin A2, CCM_CLKO2. However, I cannot achieve this using the CCM_CCOSR register. I try the following here:
- CLKO_SEL = 1111 to get the PLL4 output clk
- CLKO1_EN = 1 for enabling the output pin
and - CLK_OUT_SEL = 1 for outputting CLKO1 on CLKO2
Since I used the CLK_OUT_SEL bit, CLKO2 should now show any transition (at least any vital sign of the PLL). However, I does not :-(. This stays the same when I try any other CLKO1 clock inputs. Thus, what is the right setting of CCM_CCOSR? Should be CLKO2_EN = 0 and CLKO2_SEL[..] = XXX as another post shows ?
One more thought: When I output mmdc_clk on CLKO2 (via CCM_CLKO2 and /8 using the corresponding divider), I see a 50MHz signal on the pin. Hence the IOMUX setting is correct.
