ODT setting for i.MX6UL

[surendrajadhav]

Hello,

I am doing prelayout simulation for i.MX6UL processor with DDR3L.

However in Ref. manual I can see ODT available for all address and control lines.

Also in Hyperlynx for model selection I am not able to understand for processor why address line can be configured as input. The same is shown in attached figure.

I also could not find the list of ODT's available for data lines in reference manual. However I can see them in Hyperlynx model selector. The same shown in attached image.

Let me know if I am using the correct IBIS model for CPU.

Regards,

Surendra

[Yuri]

Hello,

  Basically, ODT feature is intended for data DQ, data strobes DQS, and data masks DM.

Address and command lines are not affected by the ODT.
   The ODT field of DRAM_ADDRxx register relates only to address lines, and really should not be used.
The MMDC PHY ODT control register is applied to configure data DQ, data strobes DQS, and data masks
DM. This register is used really for ODT configuring.

So, it is recommended to use only MMDC_MPODTCTRL register to configure ODT of i.MX6.

Have a great day,

Yuri

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