i.MX6UL data lines connection with DDR3L

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i.MX6UL data lines connection with DDR3L

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surendrajadhav
Contributor IV

Hello,

Let me know for DDR3L interface of .MX6UL, does CPU supports the pin swapping features for data lines.With this feature we can connect any of the data line (D0:16) to any of the data lines. No one to one connection is required i.e. D0 to D0, D1 to D1 and so on.

This helps us for PCB layout.

Regards,

Surendra

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Yuri
NXP Employee
NXP Employee

Hello,

  Section 3.5.1 (Swapping data lines) of  Hardware Development Guide for the i.MX 6UltraLite Applications
Processor, Rev. 1, 03/2016 states :


The DDR3 pin swapping technique for the data bus lines within bytes makes it easier to:
• Route direct lines
• Avoid changes between layers
The rules are as follows:
• Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane
by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)
— The lowest bit of each byte must be aligned between the i.MX 6UltraLite and DDR chips. For
example, D0 of i.MX 6UltraLite to D0 of DDR chip, D8 of i.MX 6UltraLite to D8 of DDR
chip.
— Other data lines free to swap within byte lane
• JEDEC DDR3 memory restrictions are:
— No restrictions for complete byte lane swapping
— DQS and DQM must follow lanes
NOTE
If byte lane swapping was done, target DDR IC register read value must be
transposed according to the data line swapping.

http://www.nxp.com/assets/documents/data/en/user-guides/IMX6ULHDG.pdf

Have a great day,

Yuri

 

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