IMX93 with CLKIN1, CLKIN2 and EXT_CLK

[altsir]

I am designing a system with IMX93 where I need to clock the enet_clk_root and enet_timer2_clk_root from external clock other than XTAL_24. According to section 70.5 of the reference manual (page 5240), I can use CLKIN1 or CLKIN2 to clock any of the system PLLs, the problem is that I cannot find how to configure the PLLs to use CLKIN1 instead od XTAL_24. Am I missing something?

Thanks!

Alexey.

[pengyong_zhang]

Hi @altsir 

CLKIN1/2 are only used for our internal testing, so its reference clock cannot be switched.

B.R

[StarryKnight04]

Designing a system based on the IMX93 requires careful selection of clock sources for various components. In particular, proper configuration of enet_clk_root and enet_timer2_clk_root is essential for ensuring stable network functionality. Discussions on the use of external clock signals such as CLKIN1, CLKIN2, and EXT_CLK are actively taking place in the NXP community.

[altsir]

Hi Daniel,

The locations in DTS file you have suggested, define which PLL is the parent for the selected Ethernet clock. (according to the datasheet, the parent for the timer1 clock can be PFD1_DIV2, PFD1_DIV2, VIDEO_PLL). I am looking for a way to set the reference clock of VIDEO_PLL (or other PLL) to be CLKIN1 instead of XTAL_24.

Thanks!

Alexey. 

[danielchen]

Hi:

The parent is PFD1_DIV2. 

Regards

Daniel

[gidame]

Daniel,

How to explain this description in the reference manual?

Let me tell you. 

CLKIN1 and CLKIN2 are designed for cases where a very precise clock is required. In this way, IMX can use a clock with the same frequency and phase as the external device.

That should be altsir's case.

[altsir]

Yes!

This is exactly my case - I need to implement PTP with SyncE for which I need two things. On the master side I need to synchronize the Ethernet transmitter and PTP timer with high accuracy external clock. The Ethernet transmitter clock, in RGMII mode, originates in MAC, so the IMX93_CLK_ENET and IMX93_CLK_ENET_TIMER2 should  be synchronized with external clock. On the slave side, the PTP timer should be synchronized with the recovered Ethernet RX clock. 

For both cases I was planning to use CLKIN1 and CLKIN2 inputs, but now it seems that those inputs are not functional as the intention was.    

[gidame]

clk_ext1 is the clock in. 

It can not only provide a clock source for the PLL. And it can be used directly in some modules.  But need to change some  code in dts.

Here is the example, SAI can use an external clock, so that it can be fully synchronized with external clocks such as codec, with exactly the same frequency and phase.

imx93-clock.h

#define IMX93_CLK_24M 1
#define IMX93_CLK_EXT1 2
#define IMX93_CLK_SYS_PLL_PFD0 3

imx93.dtsi

clk: clock-controller@44450000 {
compatible = "fsl,imx93-ccm";
reg = <0x44450000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
clock-names = "osc_32k", "osc_24m", "clk_ext1";
assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>, <&clk IMX93_CLK_VIDEO_PLL>,
  <&clk IMX93_CLK_A55>;
assigned-clock-parents = <0>, <0>, <&clk IMX93_CLK_SYS_PLL_PFD0>;
assigned-clock-rates = <393216000>, <594000000>, <500000000>;
status = "okay";
};

sai1: sai@443b0000 {
compatible = "fsl,imx93-sai";
reg = <0x443b0000 0x10000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};

[altsir]

This could work if there was a way to use EXT_CLK in Ethernet module, but it seems that EXT_CLK could be only used in SAI modules.

Thanks!

Alexey.

[altsir]

Hi!

Can I clock the PFD1_DIV2 by CLKIN1 instead of XTAL_24?

Thanks!

Alexey.

[danielchen]

@altsir 

CLKIN1/CLKIN2 is for internal test purpose.  If you need to use it, you can try to choose the source,  set the corresponding PLL frequency , please refer to the dts file.

linux-imx/arch/arm64/boot/dts/freescale/imx93.dtsi at lf-6.6.y · nxp-imx/linux-imx

Regards

Daniel

[altsir]

@danielchen 

Hi Daniel,

The locations in DTS file you have suggested, define which PLL is the parent for the selected Ethernet clock. (according to the datasheet, the parent for the timer1 clock can be PFD1_DIV2, PFD1_DIV2, VIDEO_PLL). I am looking for a way to set the reference clock of VIDEO_PLL (or other PLL) to be CLKIN1 instead of XTAL_24.

Thanks!

Alexey.