IMX8MN u-boot 2024.04 SPL DTS issue.

[mabar70]

I am working on an uplift from kirkstone (uboot-imx 2022.04) to scarthgap using IMX BSP.

System is custom based on the IMX8MN with LPDDR4.

The commit in branch of uboot-imx which is based on:
commit de16f4f17221b2ff72b8cb18c28cd8a29f3c2710 (HEAD -> lf_v2024.04, tag: lf-6.6.36-2.1.0, tag: android-14.0.0_2.2.0, origin/lf_v2024.04)

Trying to start SPL for flashing via uuu gives.
3:3>Start Cmd:SDPS: boot -f >/nix/store/dljgvki41iynrwc2l5an6l99v5pnzx2g-sign-all-the-things/flash.bin
15%3:3>Fail HID(W):LIBUSB_ERROR_TIMEOUT(1.045s)

And reading the uart output says:
U-Boot SPL 2024.04-imx_v2024.04_6.6.36-2.1.0+gde16f4f1722+p0 (Sep 02 2024 - 10:44:35 +0000)
Failed to find clock node. Check device tree

Adding some more debug to u-boot gives additional information:
clock-controller@30380000: could not find phandle, phandle: 20, cur_index: 0
clk_get_by_index_tail: Node 'clock-controller@30380000', property 'clocks', failed to request CLK index 1: -22
Failed to find clock node. Check device tree

The probe of fsl,imx8mn-ccm fails when trying to find osc_24m in DTB.
Code (clk-imx8mn.c)
ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
   if (ret) {
     return ret;
   }

Code: (fdtdec.c)
if (cells_name || cur_index == index) {

    node = fdt_node_offset_by_phandle(blob, phandle);
    if (node < 0) {
       printf("%s: could not find phandle, phandle: %d, cur_index: %d\n",
       fdt_get_name(blob, src_node, NULL), phandle, cur_index);
       goto err;
    }
}

So if I modify clk-uclass.c to not use cell_name, #clock-cells,
it will proceed a bit further but fail at other points. This is obviously not the way forward but perhaps can shed some light at whats wrong?

clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
{
    struct ofnode_phandle_args args;
    int ret;

     ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
     index, &args);

The DTS code adjacent to the error is as follows:
imx8mn.dtsi:
clk: clock-controller@30380000 {
    compatible = "fsl,imx8mn-ccm";
    reg = <0x30380000 0x10000>;
    #clock-cells = <1>;
    clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
             <&clk_ext3>, <&clk_ext4>;
    clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
                  "clk_ext3", "clk_ext4";
    assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
                      <&clk IMX8MN_CLK_A53_CORE>,
                      <&clk IMX8MN_CLK_NOC>,
                      <&clk IMX8MN_CLK_AUDIO_AHB>,
                      <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
                      <&clk IMX8MN_SYS_PLL3>,
                      <&clk IMX8MN_VIDEO_PLL1>,
                      <&clk IMX8MN_AUDIO_PLL1>,
                      <&clk IMX8MN_AUDIO_PLL2>;
    assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
                             <&clk IMX8MN_ARM_PLL_OUT>,
                             <&clk IMX8MN_SYS_PLL3_OUT>,
                             <&clk IMX8MN_SYS_PLL1_800M>;
    assigned-clock-rates = <0>, <0>, <0>,
                           <400000000>,
                           <400000000>,
                           <600000000>,
                           <1039500000>,
                           <393216000>,
                           <361267200>;
};
 
From custom device tree usage of the same node via phandle:

&clk {
  bootph-pre-ram;
  bootph-all;
  /delete-property/ assigned-clocks;
  /delete-property/ assigned-clock-parents;
  /delete-property/ assigned-clock-rates;
};

&osc_24m {
  bootph-pre-ram;
  bootph-all;
};

Something is obviously missing in this migration.
I am attaching the DTS sources.

What is the problem?
Is there some official migration guide to follow 2022->2024?
Thanks!

[AldoG]

Hello,

Could you share how you are creating/building your boot image?
Also, from where are you getting the source code?

Best regards/Saludos,
Aldo.

[mabar70 · Accepted solution]

Hi, AldoG, thanks for your reply and interest in the issue.


The code is as already stated from the uboot-imx repo pointed to from scarthgap yocto release.
:
./build/tmp/work/xbrain-poky-linux/u-boot-imx/2024.04/git
$ git status
On branch lf_v2024.04
Your branch is up to date with 'origin/lf_v2024.04'.

no changes added to commit (use "git add" and/or "git commit -a")
$ git remote -vv
origin https://github.com/nxp-imx/uboot-imx.git (fetch)
origin https://github.com/nxp-imx/uboot-imx.git (push)

latest commit:
commit de16f4f17221b2ff72b8cb18c28cd8a29f3c2710 (HEAD -> lf_v2024.04, tag: lf-6.6.36-2.1.0, tag: android-14.0.0_2.2.0, origin/lf_v2024.04)

Anyways, I found out what the problem was yesterday.
You need to specify all the clocks as bootph-all, bootph-reram in your custom DTS when cells-name is assigned. If you dont you get the issue above.
The DTS code in u-boot verifies that all the clocks in the list are active. This wasnt mandatory in 2022.04 obviously. It would be good to know all these pitfalls before a BSP migration.

DTS custom code now:

&clk {
bootph-pre-ram;
bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};

&osc_24m {
bootph-pre-ram;
bootph-all;
};

+&osc_32k {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&clk_ext1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&clk_ext2 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&clk_ext3 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&clk_ext4 {
+ bootph-pre-ram;
+ bootph-all;
+};
+

This might serve for others facing the same issue.