Hi,
I'm using imx8m custom board, linux 4.9.51 ga release.
I'm trying to implement QSPI_A and QSPI_B in imx8m platform. I'm able to add QSPI_A(alone) successfully. If I add both QSPI_A and B, the board hangs. If I try to add QSPI_B alone by disabling A, I get the below messages:
=======================================================
# dmesg | grep -i spi
fsl-quadspi 30bb0000.qspi: unrecognized JEDEC id bytes: 00, 00, 00
fsl-quadspi 30bb0000.qspi: Freescale QuadSPI probe failed
fsl-quadspi: probe of 30bb0000.qspi failed with error -2
========================================================
Following is the dts node and pin controls I'm using.
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash0: mt25qu256aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt25qu256aba";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <12000000>;
spi-nor,ddr-quad-read-dummy = <6>;
status="okay";
};
flash1: mt25qu256aba@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt25qu256aba";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <12000000>;
spi-nor,ddr-quad-read-dummy = <6>;
status = "okay";
};
};
....
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82
MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82
MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82
>;
};
Is this correct? There is no clock when I probe. Is there anything which is needed to be added to enable QSPI_B apart from the dts?
Thanks in advance.
Regards,
Prajna
please check the chapter 10.2.3.4. There are the Memory Map of Flash A and B in the i.MX8M RM.
Hi Jimmychan,
Thanks for the reply. Is there any change to be done in dts or driver file? If yes, what are the changes?
Regards,
Prajna
Did you use symmetric NOR chips?
for example:
If two chips(or two planes in one die) are symmetric, the driver should work fine, please follow the i.MX6SX dtb settings below:
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
status = "okay";
ddrsmp=<2>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <1>;
};
};