How to configure a new SDRAM on RT1170

[yalin]

I'd like to use a new SDRAM IS42S16160J to replace the original one W9825G6KH-5I on the MIMXRT1170-EVK, is there any referrence for what configuration I need to modify?

Thanks.

[jay_heng]

You can refer to below configuration (it is for RT10xx device, for RT1170, the peripheral register base address might be changed)

https://github.com/JayHeng/NXP-MCUBootUtility/tree/master/src/targets/dcd_model/ISSI_IS42S16160J

[yalin]

@jay_heng Thanks for support.

About the dcd.cfg you mentioned, I have the following questions.

1.Where should the dcd.cfg be used? I don't find it in RT1170 project.

2.Does it correspond to board/dcd.c in RT1170 project?

3.What is the meaning of registers in dcd.cfg, is there any document for reference?

Thanks.

[jay_heng]

dcd.cfg file is used to generate dcd.c. imgutil.exe tool can do this job

the content in dcd.cfg are all register (IOMUXC, SEMC, CCM) configuration sequences. you can refer to them to learn IS42S16160J configuration

[yalin]

@jay_heng Thanks for support.

1. imgutil.exe tool can only convert dcd.cfg file to dcd.bin file, but not dcd.c, is that right? I just see the command description like the following.

        Usage: imgutil <--combine/--fcb_gen/--dcd_gen> <Parameters> [Options]

        3. Arguments for '--dcd_gen' :
        Mandatory paramters:
        dcd_desc_file=<dcd desc file>

        ofile=<output dcd binary file>

2. Or do you mean I can configure my dcd.c according to your dcd.cfg of IS42S16160J? If so, I need to modify just the SEMC registers or all registers in dcd.c according to dcd.cfg for using IS42S16160J.

Thanks.

[yalin]

@jay_hengI have my new board with the new sdram IS42S16160J now, and I run the SDK evkmimxrt1170_semc_cm7 by modifying some parameter in BOARD_InitSEMC(), and the log shows "Write and Read Compare Succeed". But when I run the SDK evkmimxrt1170_hello_world_demo_cm7, which use BOARD_SDRAM as default RAM, the program can't jump to main() function after flashing, and then 'Break at address "0xdeadbeee" '.

1. I use the downloading algorithm 'MIMXRT1170_UFL_L2' for hyperflash S26KS512 and modify WorkRAMAddr="0x80000000" in JLinkDevices.xml for running SDK evkmimxrt1170_hello_world_demo_cm7, does this lead to the above problem? Is there any mismatch issue when using the JLinkScript of  'MIMXRT1170_UFL_L2' and sdram as default RAM together?

2. If not, is there any other modification needed besides the register in dcd.c if using a new sdram?

Thanks.

[sajithdevidas]

 what changes did you made on BOARD_InitSEMC()?, im also neede to configure IS45S32160F with rt1170 microcontroller, can you help me?

[yalin]

In a sdram test board with IS42, I just modify the following two parameters, and the log shows "Write and Read Compare Succeed"

sdramconfig.memsize_kbytes = 32 * 1024; /* 64MB = 2*32*1024*1KBytes*/
sdramconfig.portSize = kSEMC_PortSize16Bit; /*two 16-bit SDRAMs make up 32-bit portsize*/

But now I have a formal product board with IS45, the log shows "Write and Read Compare Failed" with the same configuration as IS42, I'm not sure it's a software or hardware problem now. I think IS42 and IS45 looks like same.

Can you read and write IS45 normally now?