Specifically I'm looking at the imx6qdl-sabresd.dtsi file and the ecspi1 node, below is the relevant snippet:
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
This node uses a property "cs-gpios" which is saying we're using GPIO4 with Mux option IO09 as a Chip Select for ECSPI1. However when we examine the pinctrl_ecspi1 node:
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
There is no MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 setup. From the SABRE schematics we can see "KEY_ROW1__CSPI1_CS0" is being used, which implies the pin group should have had MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 should have been configured and cs-gpios shouldn't have been used at all, but that's not the case either.
So my questions:
1) Is the pinctrl_ecspi1 group incorrect? (missing the Chip Select pin configuration) or is that done somewhere else?
2) Is chip select done by mux option ECSPI1_SS0 (as shown in the schematics) or is it done by GPIO4 (as implied by the use of cs-gpios)?
3) If chip select for ECSPI1 is via ECSPI1_SS0 is it correct to remove the cs-gpios property from this node?
Hi Michael.
The Device Tree is configuring that pin as GPIO because it is handled manually. if you want to configure the pin to be handled automatically by the SPI module you need to make so modications. So, regarding to your question.}
1) No, it is not wrong, the configuration is set to handle Chip Select manually.
2) Is by GPIO 4
3) To set the Chip Select for automatic functionality
a) change fsl,spi-num-chipselects to 0. E.g. fsl,spi-num-chipselects = <0>;
b) remove line cs-gpios = <&gpio4 9 0>;
c) Add MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 in pinctrl_ecspi1: ecspi1grp
Hope this helps,
Regards,
Carlos
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