Documentation for SCU_PMIC_MEMC_ON pin at iMX8QM

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Documentation for SCU_PMIC_MEMC_ON pin at iMX8QM

ソリューションへジャンプ
1,058件の閲覧回数
K_Steinhammer
Contributor III

Can someone give me a hint where the function of the SCU_PMIC_MEMC_ON pin on the iMX8QM is documented?

I can't find a anything in the Reference Manual or in the Datasheet except pin name and pin configuration, but no description for function or timing.

In the MEK schematic it is involved in reset generation for peripherals, but that's all I could find.

 

0 件の賞賛
返信
1 解決策
1,050件の閲覧回数
Yuri
NXP Employee
NXP Employee

@K_Steinhammer 
Hello,

  SCU_PMIC_MEMC_ON "is intended as a control signal to switch on group 2 power rails, but only
for non-standard PMIC solutions, which we have not validated to date. If using our intended PMIC solution (PF8100/8200), which predominantly use I2C for control, then SCU_PMIC_MEMC_ON is effectively a don't care signal and can be left not connected."

Regards,
Yuri.

 

元の投稿で解決策を見る

1 返信
1,051件の閲覧回数
Yuri
NXP Employee
NXP Employee

@K_Steinhammer 
Hello,

  SCU_PMIC_MEMC_ON "is intended as a control signal to switch on group 2 power rails, but only
for non-standard PMIC solutions, which we have not validated to date. If using our intended PMIC solution (PF8100/8200), which predominantly use I2C for control, then SCU_PMIC_MEMC_ON is effectively a don't care signal and can be left not connected."

Regards,
Yuri.