Hello,
Sources of the SSI_CLK_ROOT (PLL4, PLL3) are shown on Figure 18-2 (Clock Tree - Part 1)
of the I.MX6 S/DL RM. Strictly speaking, jitter, accuracy, duty parameters of internal PLLs are not specified.
The only specified parameters may be found in the Datasheet(s) in section “PLL’s Electrical Characteristics”.
Nevertheless, we can refer to 24 MHz crystal tolerance guidelines of the Hardware Development Guide, assuming stability (thermal, voltage and other) of PLL output clock is fully defined
by external crystal / oscillator in order to meet USB, PCIe, Ethernet clock specs.
Have a great day,
Yuri
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
