This article discusses the different use cases and configuration of the errata "ERR053377: FlexCAN: Message Buffer (MB) and Enhanced RX FIFO Filter Element (ERFFEL) Memory Corruption". The errata is impacting Messabe Buffers (MB) and Enhanced RX FIFO Filter Elements (ERFFEL), the impact of each MB or ERFFEL depends on the configuration of the payload buffer, MB and/or ERFFEL. In this post, we plan to provide some examples of such configuration and impact on the FlexCAN IP.
Taking a 64-byte payload as an example, the following configurations illustrate the trade-off between the number of Message Buffers (MBs) and acceptance filters:
/* ERR053377: This errata explains affected words depends on MB payload size, this example applies for MB configured for 64-byte payload */
#define BYTES_IN_MB kFLEXCAN_64BperMB
FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true);
1. MB0 is not used, MB1 is used. In this configuration, ERFFEL[0–29] can be fully utilized as acceptance filters, while MB1–MB6 are available as Message Buffers, maximum ERFCR[NFE] is 14. The following code can be used as reference for the driver configuration for this case.
/* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x140. Used ERFFEL[0–29], ERFCR[NFE]=14 */
uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0)};
flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig;
flexcan_rx_mb_config_t mbConfig;
/* Setup Enhanced Rx FIFO. */
rxEhFifoConfig.idFilterTable = rxEnFifoFilter;
rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U;
rxEhFifoConfig.extendIdFilterNum = 0;
rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */
rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead;
rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh;
FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true);
rxFifoXfer.framefd = &rxFrame[0];
rxFifoXfer.frameNum = RX_MESSAGE_COUNT;
/* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */
FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0));
#define RX_MESSAGE_BUFFER_1 (1U)
/* Setup Rx Message Buffer 1. */
mbConfig.format = kFLEXCAN_FrameFormatStandard;
mbConfig.type = kFLEXCAN_FrameTypeData;
mbConfig.id = FLEXCAN_ID_STD(0x121U);
FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true);
2. MB0 and MB1 are not used. In this case, ERFFEL[0–31] are available for acceptance filtering, and MB2–MB6 are reserved as Message Buffers, maximum ERFCR[NFE] is 15. The following code can be used as reference for the driver configuration for this case.
/* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x142. Used ERFFEL[0–31], ERFCR[NFE]=15 */
uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x141, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x142, 0, 0x3F, 0)};
flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig;
/* Setup Enhanced Rx FIFO. */
rxEhFifoConfig.idFilterTable = rxEnFifoFilter;
rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U;
rxEhFifoConfig.extendIdFilterNum = 0;
rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */
rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead;
rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh;
FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true);
rxFifoXfer.framefd = &rxFrame[0];
rxFifoXfer.frameNum = RX_MESSAGE_COUNT;
3. MB0 and MB1 are both used. Under this configuration, only ERFFEL[0–11] can be used as acceptance filters. ERFFEL[12–31] are not available, while MB0–MB6 can be used as Message Buffers, maximum ERFCR[NFE] is 5. The following code can be used as reference for the driver configuration for this case.
/* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x12E. Used ERFFEL[0–11], ERFCR[NFE]=5 */
uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0),
FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0)};
flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig;
flexcan_rx_mb_config_t mbConfig;
/* Setup Enhanced Rx FIFO. */
rxEhFifoConfig.idFilterTable = rxEnFifoFilter;
rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U;
rxEhFifoConfig.extendIdFilterNum = 0;
rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */
rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead;
rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh;
FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true);
rxFifoXfer.framefd = &rxFrame[0];
rxFifoXfer.frameNum = RX_MESSAGE_COUNT;
/* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */
FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0));
#define RX_MESSAGE_BUFFER_0 (0U)
/* Setup Rx Message Buffer 0. */
mbConfig.format = kFLEXCAN_FrameFormatStandard;
mbConfig.type = kFLEXCAN_FrameTypeData;
mbConfig.id = FLEXCAN_ID_STD(0x120U);
FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_0, &mbConfig, true);
#define RX_MESSAGE_BUFFER_1 (1U)
/* Setup Rx Message Buffer 1. */
mbConfig.format = kFLEXCAN_FrameFormatStandard;
mbConfig.type = kFLEXCAN_FrameTypeData;
mbConfig.id = FLEXCAN_ID_STD(0x121U);
FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true);
Recommendation: To achieve a balanced trade-off between the number of Message Buffers and acceptance filters, Option 1 is recommended.
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