This post provides guidance on how to update the NBU firmware on MCX W72 and KW47 devices through several methods: Bootloader Host Application (blhost), Secure Provisioning Tool, LinkServer. The Narrow Band Unit (NBU) is a dedicated compute subsystem for the Narrowband Radio, present in select NXP wireless microcontrollers. It is comprised of an Arm® Cortex®-M33 and associated peripherals that, in conjunction with the Bluetooth Unit, support the Bluetooth LE protocol. Running at 96 MHz alongside a 2.4 GHz transceiver, the NBU operates independently from the main application core, offloading all radio processing from the primary CPU and freeing it for application tasks. While the NBU allows for flexibility for evolving requirements, firmware to implement radio protocols is intended to be developed and delivered by NXP. Note: It is important that the NBU firmware version matches the SDK version of the application. After downloading the SDK and before running any wireless examples, update the NBU firmware using the binaries provided in the SDK folder. The NBU binary file is located in the SDK folder. Go to the SDK root folder and open the path: path_to_SDK\mcuxsdk\middleware\wireless\ble_controller\bin   Prerequisites To follow this guide, the following environment is required: Software Setup Bootloader Host Application (blhost). Download here. MCUXpresso Secure Provisioning Tool. Download here. LinkServer for Microcontrollers. Download here. Hardware Setup Development boards associated with the MCX W72 or KW47 microcontroller families may be used. The ISP button varies by board and is referred to as ISP_button  throughout this guide: Development board ISP_button FRDM-MCXW72 SW3 MCXW72-LOC SW4 KW47-EVK SW4 KW47-LOC SW4   To set the board to the Bootloader ISP mode, press and hold the ISP_button , connect the development board via the MCU-Link connector to the PC, then release ISP_button .   Bootloader Host Application (blhost) Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. Verify the COM port assigned to the board by opening Device Manager in Windows and searching for Ports (COM & LPT). Identify and note the corresponding COM port number. Open a command prompt and change the directory to the location of the blhost.exe file: (BLHost_root_location)\blhost_2.6.7\bin\win Verify communication by running the following command, making sure to replace COMX with the COM port assigned to your device: blhost.exe -p COMX get-property 1 Update the NBU firmware image. First, erase the NBU memory: blhost.exe -p COMX flash-erase-all 2 Write the new firmware image using the following command. The write-memory command uses 0x48800000 as the start address, which corresponds to the NBU memory base. Provide the full path to the binary file, or alternatively, copy the .bin file into the same directory as blhost.exe to simplify the command: blhost.exe -p COMX write-memory 0x48800000 <nbu_binary>.bin sofiaurueta_0-1784588034793.png   MCUXpresso Secure Provisioning Tool Create a workspace for the device. To use the keys same as the development board, select the processor relevant to the FRDM/EVK board. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. To verify communication, click the UART tab, refresh the Port field selection and select the assigned COM Port identified. Click Test connection and confirm that the result displays OK. In the toolbar, select the boot type as Plain unsigned or Plain with CRC. In the Build Image view, load the binary file in Source executable image, enter the start address as  0x48800000  (which corresponds to the NBU memory base), and click Build image. SECTool_1.jpg Navigate to the Write Image view, select Use built image, and click Write image. SECTool_2.jpg A success message appears when the NBU firmware loading is complete.   LinkFlash Tool For this method, a LinkServer debug probe must be available on the board. The steps on how to install the CMSIS-DAP/SEGGER J-link firmware are available here. Navigate to the main LinkServer folder in your computer and execute the  LinkFlash.exe  file. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. In the LinkFlash tool, after the device is connected, click the Refresh button to update and set the probe target of the board. Go to the Program tab, click Browse, select the NBU firmware file, and enter the start address  0x48800000 . Ensure to check the boxes Mass erase before programming and Reset target after programming. To load the NBU firmware, click Program. LinkFlashTool.jpg  

This article discusses the different use cases and configuration of the errata "ERR053404: FlexCAN: Message Buffer (MB) and Enhanced RX FIFO Filter Element (ERFFEL) Memory Corruption". The errata is impacting Messabe Buffers (MB) and Enhanced RX FIFO Filter Elements (ERFFEL), the impact of each MB or ERFFEL depends on the configuration of the payload buffer, MB and/or ERFFEL. In this post, we plan to provide some examples of such configuration and impact on the FlexCAN IP.  Taking a 64-byte payload as an example, the following configurations illustrate the trade-off between the number of Message Buffers (MBs) and acceptance filters: /* ERR053404: This errata explains affected words depends on MB payload size, this example applies for MB configured for 64-byte payload */ #define BYTES_IN_MB kFLEXCAN_64BperMB FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); 1. MB0 is not used, MB1 is used. In this configuration, ERFFEL[0–29] can be fully utilized as acceptance filters, while MB1–MB6 are available as Message Buffers, maximum ERFCR[NFE] is 14. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x140. Used ERFFEL[0–29], ERFCR[NFE]=14 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); 2. MB0 and MB1 are not used. In this case, ERFFEL[0–31] are available for acceptance filtering, and MB2–MB6 are reserved as Message Buffers, maximum ERFCR[NFE] is 15. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x142. Used ERFFEL[0–31], ERFCR[NFE]=15 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x141, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x142, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; 3. MB0 and MB1 are both used. Under this configuration, only ERFFEL[0–11] can be used as acceptance filters. ERFFEL[12–31] are not available, while MB0–MB6 can be used as Message Buffers, maximum ERFCR[NFE] is 5. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x12E. Used ERFFEL[0–11], ERFCR[NFE]=5 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_0 (0U) /* Setup Rx Message Buffer 0. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x120U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_0, &mbConfig, true); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); Recommendation: To achieve a balanced trade-off between the number of Message Buffers and acceptance filters, Option 1 is recommended.

The clock tolerance for CAN FD at high baud rates is generally considered to be tight compared to lower baud rates, meaning that the clock frequency needs to be very precise to ensure reliable communication; this is due to the high data rate requiring precise bit timing. CAN generally requires crystal or PLL clock source due to accuracy requirements, on KW45/7 that is limited to 32 MHz crystal (SOSC) since there is no PLL available. However, the FRO192 (FIRC) can be fine trimmed to the SOSC crystal as reference, in a closed loop configuration. When operating in closed loop the FRO192 accuracy is +/-0.25%. The FRO192 when operating in open loop (default) will not be accurate enough for CAN-FD (+/-3%). Closed loop operation is enabled while SCG0→FIRCCSR[FIRCTRUP] = 1 and SCG0→FIRCCSR[FIRCTREN] =1. The auto trim continues as long as those bits are set (for example if change in temperature causes the FRO192clock frequency to drift). Once locked, only the fine trim bits would be updated on subsequent corrections. Refer to code snippet below for correct clock configuration: #include "clock_config.h" #include "fsl_clock.h" const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = { .freq = 32000000U, /* System Oscillator frequency: 32000000Hz */ .monitorMode = kSCG_SysOscMonitorDisable, /* System OSC Clock Monitor is disabled */ .enableMode = kSCG_SoscEnable, /* System OSC Enable */ }; const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = { .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ .src=(uint32_t)kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */ }; static const scg_firc_trim_config_t FircTrimConfig_BOARD_BootClockRUN = { .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ .trimsrc=kSCG_FircTrimSrcSysOsc, /* Trim source is System OSC */ .trimDiv = 31U, /* Divided by 32 */ .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ .trimFine = 0U, /* Trim value, see Reference Manual for more information */ }; const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = { .enableMode = kSCG_FircEnable, /* Fast IRC is enabled */ .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ .trimConfig = &FircTrimConfig_BOARD_BootClockRUN, }; /* Unlock FIRC and SOSC control status registers */ CLOCK_UnlockFircControlStatusReg(); CLOCK_UnlockSysOscControlStatusReg(); /* Init FIRC */ CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN); /* Set SCG to FIRC mode */ CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN); /* Wait for clock source switch finished */ do { CLOCK_GetCurSysClkConfig(&curConfig); } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src); /* Initializes SOSC according to board configuration */ (void)CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN); /* Set the XTAL0 frequency based on board settings */ CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq); /* For 6 mbps baud rate requires FRO192M as FlexCAN source clock */ CLOCK_SetIpSrc(kCLOCK_Can0, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Can0, kSCG_SysClkDivBy1); The maximum supported baud rate for KW47 and MCXW72 devices is 6 Mbps. Although higher rates may be achievable on some SoCs, 6 Mbps is the highest baud rate supported by the device clock specifications.  For simplicity, the FlexCAN driver APIs can be used to configure the CAN FD baud rate, as shown in the following code snippet: #include "fsl_flexcan.h" #define EXAMPLE_CAN CAN0 #define USE_CANFD (1) #define RX_MESSAGE_BUFFER_NUM (0) #define TX_MESSAGE_BUFFER_NUM (1) #define BYTES_IN_MB kFLEXCAN_64BperMB /* For 6 Mbps use case. FRO192 must be selected as clock source */ #define EXAMPLE_CAN_CLK_FREQ CLOCK_GetFreq(kCLOCK_ScgFircClk) #define USE_IMPROVED_TIMING_CONFIG (1) flexcan_config_t flexcanConfig; /* Get FlexCAN module default Configuration. */ /* * flexcanConfig.clksrc=kFLEXCAN_ClkSrc0; * flexcanConfig.bitRate = 1000000U; * flexcanConfig.bitRateFD = 2000000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.disableSelfReception = false; * flexcanConfig.enableListenOnlyMode = false; * flexcanConfig.enableDoze = false; */ FLEXCAN_GetDefaultConfig(&flexcanConfig); /* Manually override default CAN FD config to 1 Mbps for nominal rate and 6 Mbps for data rate */ flexcanConfig.bitRate = 1000000U; flexcanConfig.bitRateFD = 6000000U; #if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) flexcan_timing_config_t timing_config; memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, EXAMPLE_CAN_CLK_FREQ, &timing_config)) { /* Update the improved timing configuration*/ memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); } #endif FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); Note: The maximum supported CAN baud rate for KW47 and MCXW72 devices is 2 Mbps. While higher rates may be achievable under certain conditions, operation above 2 Mbps is outside the supported specification and is not recommended for applications in the field. 

In default, IMX95-19x19 EVK board enables the PCIe M.2 interface for Wi-Fi modules. But for SDIO interface M.2 Wi-Fi module, we could not use it directly. This doc is a step by step guide about how to make IW612 SDIO M.2 module(Murata 2EL) working on IMX95-19x19 EVK board based on Android 16. 1.Download I.MX Android BSP package, copy with scp to VMSIS. 16.0.0_1.4.0_ANDROID_SOURCE 2.Decompressing android bsp tar -xzf imx-android-16.0.0_1.4.0.tar.gz 3. source ./imx_android_setup.sh to download Android source code. 4.Prepare cross compiler GCC cross compiler: Download the tool chain for the AArch32 and AArch64 on: Arm GNU Toolchain I download the latest version: Arm GNU Toolchain 15.3.rel1 Need to pay attention, for I.MX95, need both 64 bit and 32 bit GCC compile tool. 64bit: arm-gnu-toolchain-15.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz 32 bit: arm-gnu-toolchain-15.3.rel1-x86_64-arm-none-eabi.tar.xz For AArch64 toolchain nxf93258@lsv051430:~/GCC_cross_compile_toolchain$sudo tar -xvJf arm-gnu-toolchain-15.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz -C /opt/ nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$export AARCH64_GCC_CROSS_COMPILE=/opt/arm-gnu-toolchain-15.3.rel1-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu- For 32bit toolchain: nxf93258@lsv051430:~/GCC_cross_compile_toolchain$sudo tar -xvJf arm-gnu-toolchain-15.3.rel1-x86_64-arm-none-eabi.tar.xz -C /opt/ nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ export AARCH32_GCC_CROSS_COMPILE=/opt/arm-gnu-toolchain-15.3.rel1-x86_64-arm-none-eabi/bin/arm-none-eabi- 5.Set the external clang, kernel-build-tools, rust, and clang-tools tools for kernel building: nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ sudo ./device/nxp/common/tools/setup_android_kernel_prebuilts.sh 6.Set up the environment for building. This only configures the current terminal, if change to another terminal need to re-run the configurations. nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ source build/envsetup.sh 7.Execute the Android lunch command for i.MX95-EVK. nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$lunch evk_95-nxp_stable-userdebug 8.Optional Steps: Execute the imx-make.sh script to finish the whole images compiling. Or you can follow below steps to only build required images. nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ ./imx-make.sh -j4 2>&1 | tee build-log.txt 9.Modify the device tree to disable pcie0 and enable usdhc3 like below: ~/Android/imx-android-16.0.0_1.4.0/android_build/vendor/nxp-opensource/kernel_imx/arch/arm64/boot/dts/freescale$ git diff diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 69508a66f1c8..dfa1d3d51a9c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -26,10 +26,19 @@ / { aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &lpuart1; ethernet0 = &enetc_port0; ethernet1 = &enetc_port2; }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + post-power-on-delay-ms = <100>; + }; + bt_sco_codec: audio-codec-bt-sco { #sound-dai-cells = <1>; @@ -651,7 +660,7 @@ &pcie0 { reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; vpcie-supply = <&reg_pcie0>; supports-clkreq; - status = "okay"; + status = "disable"; }; &pcie1 { @@ -733,6 +742,22 @@ &usdhc2 { status = "okay"; }; +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <&reg_pcie0>; //Both PCIE0 and USDHC3 use same power supply. + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + + &enetc_port0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enetc0>; @@ -1225,6 +1250,45 @@ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseq { + fsl,pins = < + IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; }; &thermal_zones { 10.Build dtbo image. Need about 40 minutes. DTBO image holds the device tree binary of the board. nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ source build/envsetup.sh nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$ lunch evk_95-nxp_stable-userdebug nxf93258@lsv051430:~/Android/imx-android-16.0.0_1.4.0/android_build$./imx-make.sh dtboimage -j4 Then you will see that the dtbo images time stamp are updated as below: Christine_Li_0-1786168405295.png Below info is for your reference. ~/Android/imx-android-16.0.0_1.4.0/android_build/device/nxp/common/build/dtbo.mk This makefile includes the logic how to pack dtbo image. ~/Android/imx-android-16.0.0_1.4.0/android_build/device/nxp/imx9/evk_95/SharedBoardConfig.mk Christine_Li_1-1786168463709.png  This Macro: SUPPORT_GBL is not enabled in default, so still use dtbo image for the device tree. ~/Android/imx-android-16.0.0_1.4.0/android_build/device/nxp/imx9/evk_95/BoardConfig.mk Christine_Li_2-1786168477241.png  Wi-Fi/Bluetooth FW located here: Christine_Li_3-1786168507234.png  Wi-Fi/Bluetooth driver located here: Christine_Li_4-1786168518852.png Can modify the Makefile accordingly if needed. After compiled, the Wi-Fi driver and cfg80211.ko is located here: Christine_Li_5-1786168540709.png 11.Download prebuilt Image and decompress it. 16.0.0_1.4.0_DEMO_95//Pay attention to the version, need to match with our Android Source code download version. 12.Replace dtbo image. Rename the original dtbo-imx95.img to dtbo-imx95_original.img in the prebuilt image directory to be a backup. Then copy the dtbo-imx95.img from the remote android source code compiled directory: ~/Android/imx-android-16.0.0_1.4.0/android_build/out/target/product/evk_95/dtbo-imx95.img to the prebuilt image directory. Like below: Christine_Li_6-1786168893998.png   13.Flash images into board. Change the I.MX95-19*19-EVK board's SW7 to 1001 (from 1-4 bit) to enter serial download mode, then connect the board's USB1 port with type C cable to Windows PC. Download the UUU binary file from GitHub: Releases · nxp-imx/mfgtools Open the cmd interface in administrator mode, and enter to the prebuilt image directory. Flash the images into I.MX95-19*19-EVK board with below command: uuu_imx_android_flash.bat -f imx95 -a -e -u trusty-dual For the details of each parameter, can refer to: Android Quick Start Guide 14.Verify Wi-Fi and Bluetooth functions. After flash finished successfully, power off the board and change the board's SW7 to switch the board back to 1010 (form 1-4 bit) to enter eMMC boot mode. Check dmesg logs to confirm IW612 Wi-Fi driver is loaded successfully: Christine_Li_7-1786169134244.png   Check Wi-fi and Bluetooth work as expected in UI.  Can use this application: scrcpy on windows instead of connecting a LCD. Christine_Li_8-1786169192905.png Christine_Li_9-1786169200898.png This guide can also be a reference for other M.2 Wi-Fi modules with SDIO interface working on I.MX95 19*19-EVK board with Android or Linux OS. Reference: Android Quick Start Guide Android User's Guide Linux-Kernel Archive: [PATCH V3 2/3] arm64: dts: imx95-15x15-evk: Disable PCIe bus in the default dts   Finished by Christine.Li. Aug 5 2026.

To generate a hello world (suppose) example for KW47-EVK for IAR toolchain. We asume that IAR toolchain is already installed. Set IAR_DIR environment variable. In Windows, this can be done via Edit environment variables system option. Example: IAR_DIR=C:\iar\ewarm-9.60.1.    Note: IAR toolchain version may change. Type the following commands on your MCUXSDK workspace: cd mcuxsdk west build -b kw47evk ./examples/demos_apps/hello_world --toolchain=iar -t standalone_project -Dcore_id=cm33_core0 --pristine -d ./build/kw47evk/kw47evk_standalone_hello_world_iar​ IAR project should have been generated on  MCUXSDK_WS/mcuxsdk/build/kw47evk/kw47evk_standalone_hello_world_iar/iar directory. IAR project has .eww file extension.  neidys_vargas_0-1784665664365.png    Relevant links IDE Project Generation: https://mcuxpresso.nxp.com/mcuxsdk/latest/html/develop/build_system/IDE_Project.html# Note: Ruby is required for this feature. Typically, this tool is installed via MCUXpresso Installer. However, if having issues with this tool refer to the next link: Ruby Environment Setup: https://mcuxpresso.nxp.com/mcuxsdk/latest/html/develop/build_system/IDE_Project.html#ruby-environment-setup Suppose you want to generate a hello world example for KW47-EVK for IAR toolchain as the previous example, but this time LPTMR driver is required for low-power timer operating purposes. We asume that IAR toolchain is already installed and IAR_DIR variable is already set. The easiest way to accomplish this is to add the lptmr Kconfig symbols with ‘yes’ value at Board-Application level (Refer to Kconfig User Guide). In this case, the target prj.conf file is located on  MCUXSDK_WS/mcuxsdk/examples/_boards/kw47evk/demo_apps/hello_world.​ Edit this file and add the LPTMR required symbols:  CONFIG_MCUX_COMPONENT_driver.lptmr=y CONFIG_MCUX_COMPONENT_component.lptmr_adapter=y​   neidys_vargas_4-1784665984531.png   neidys_vargas_1-1784665840673.png   Type the following command on your MCUXSDK workspace:  west build -b kw47evk ./examples/demo_apps/hello_world --toolchain=iar -t standalone_project -Dcore_id=cm33_core0 --pristine -d ./build/kw47evk/kw47evk_standalone_hello_world_iar IAR project should have been generated on MCUXSDK_WS/mcuxsdk/build/kw47evk/kw47evk_standalone_hello_world_iar/iar directory. IAR project has .eww file extension. This time LPTMR drivers should be included in iar/drivers/lptmr   neidys_vargas_2-1784665938476.png  neidys_vargas_3-1784665959007.png   neidys_vargas_5-1784666017506.png    

When performing Bluetooth LE RF testing on KW47 and MCXW72 devices, it may be necessary to configure the transmitter output power through a vendor-specific HCI command. NXP's Test Tool provides a convenient way to send HCI commands during Direct Test Mode (DTM) validation and characterization. Although the Test Tool is still commonly referenced in documentation and application workflows, it is no longer actively maintained. As a result, the default HCI command XML definitions included with the tool do not correctly support the vendor-specific Tx power command required by KW47 and MCXW72 devices. The default Test Tool XML does not correctly define the vendor-specific HCI_VENDOR_CONFIG_TX_POWER command for KW47 and MCXW72 devices. As a result, the command is not available in the GUI. Edit BLE HCI 5.0 1.6.1.xml (typically located in C:\nxp\Test Tool 12.9.2.2\Xml) and replace the command definition with the XML snippet provided in this article. Alternatively, replace the original XML file with the updated file attached to this article. <Vendor_Commands> <GroupDesc>Vendor_Commands</GroupDesc> <Cmd> <CmdName>HCI_VENDOR_CONFIG_TX_POWER</CmdName> <CmdDesc>HCI_VENDOR_CONFIG_TX_POWER Desc. OgB: FD OcB: 2D </CmdDesc> <CmdSync>01</CmdSync> <CmdHeader>3F 012D</CmdHeader> <CmdParms> <Parm> <ParmName>tx_power</ParmName> <ParmDesc>tx_power Desc</ParmDesc> <ParmSize>1</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> <Parm> <ParmName>Channel</ParmName> <ParmDesc>type Desc</ParmDesc> <ParmSize>1</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> <Parm> <ParmName>NotUsed</ParmName> <ParmDesc>Not Used</ParmDesc> <ParmSize>2</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> </CmdParms> </Cmd> </Vendor_Commands>​ After updating the XML file and restarting Test Tool, HCI_VENDOR_CONFIG_TX_POWER should appear in the GUI. Victor_Cubas_0-1784242948275.png HCI_VENDOR_CONFIG_TX_POWER command parameters: tx_power[1]: Supported values are 0x00 (0 dBm), 0x07 (7 dBm), and 0x0A (10 dBm). Channel[1]: Supported values are 0x00 (applies to advertising channels) and 0x01 (applies to non-advertising channels). NotUsed[2]: Reserved parameter. Always set this field to 0x0000.

This document takes i.MXRT 1060 evkc and iw610 M.2 module as example to share how to setup manufactory mode in i.MXRT platform for NXP wifi product.  Hardware Host platform: i.MXRT 1060 evkc Wi-Fi chip: iw610 M.2 evk Software RT1060EVKC SDK 25.12.00 MFG TOOL: MFG-SD-IW610-MF-LABTOOL-Native-BRG-WIN-X86-2.0.0.39.0-18.80.5.p77

This doc is a brief step by step introduction for how to play music through A2DP on IW612 + I.MX8MPlus-EVK based on L6.6.52. Step 1: Load WiFi/Bluetooth Driver • NXP i.MX Release Distro 6.6-scarthgap imx8mpevk ttymxc1 imx8mpevk login: root root@imx8mpevk:~# modprobe moal mod_para=nxp/wifi_mod_para.conf root@imx8mpevk:~# root@imx8mpevk:~# dmesg | grep wlan [ 562.728200] wlan: Loading MWLAN driver [ 562.728788] wlan: Register to Bus Driver... [ 562.730460] wlan: Enable TX SG mode [ 562.730464] wlan: Enable RX SG mode [ 563.554778] wlan: uap%d set max_mtu 2000 [ 563.622367] wlan: version = SDIW612---18.99.3.p21.10-MM6X18505.p4-GPL-(FP92) [ 563.625611] wlan: Register to Bus Driver Done [ 563.625622] wlan: Driver loaded successfully root@imx8mpevk:~#modprobe btnxpuart root@imx8mpevk:~# hciconfig -a hci0: Type: Primary Bus: UART BD Address: D0:17:69:EE:71:4F ACL MTU: 1021:7 SCO MTU: 120:6 DOWN RX bytes:774 acl:0 sco:0 events:48 errors:0 TX bytes:496 acl:0 sco:0 commands:47 errors:0 Features: 0xbf 0xfe 0x8f 0xfe 0xdb 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT • Step 2: Up BT interface and enable the power save feature root@imx8mpevk:~# hciconfig hci0 up root@imx8mpevk:~# hciconfig hci0 piscan root@imx8mpevk:~#hciconfig hci0 noencrypt root@imx8mpevk:~# hciconfig -a hci0: Type: Primary Bus: UART BD Address: D0:17:69:EE:71:4F ACL MTU: 1021:7 SCO MTU: 120:6 UP RUNNINGPSCAN ISCAN RX bytes:1900 acl:0 sco:0 events:109 errors:0 TX bytes:1365 acl:0 sco:0 commands:108 errors:0 Features: 0xbf 0xfe 0x8f 0xfe 0xdb 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT Name: 'imx8mpevk' Class: 0x200000 Service Classes: Audio Device Class: Miscellaneous, CI Version: 5.4 (0xd) Revision: 0x8300 LMP Version: 5.4 (0xd) Subversion: 0x1015 Manufacturer: NXP Semiconductors (formerly Philips Semiconductors) (37) • Step 3: Scan, Pair and Connect to Headset root@imx8mpevk:~# bluetoothctl hci0 new_settings: powered connectable discoverable bondable ssp br/edr le secure-conn cis-central cis-peripheral Agent registered [CHG] Controller D0:17:69:EE:71:4F Pairable: yes [bluetooth]# power on Changing power on succeeded [bluetooth]# default-agent Default agent request successful [bluetooth]# agent on Agent is already registered [bluetooth]# scan on [NEW] Device B1:96:11:68:9C:09 联想thinkplus-HE05X II代 [bluetooth]# scan off [bluetooth]# pair B1:96:11:68:9C:09 Attempting to pair with B1:96:11:68:9C:09 hci0 device_flags_changed: B1:96:11:68:9C:09 (BR/EDR) supp: 0x00000000 curr: 0x00000000 [DEL] Device 67:02:B9:7C:ED:B5 67-02-B9-7C-ED-B5 [DEL] Device 80:F4:16:4C:48:F2 HI-Apiyoo-12MIQ001981 hci0 B1:96:11:68:9C:09 type BR/EDR connected eir_len 34 [CHG] Device B1:96:11:68:9C:09 Connected: yes hci0 new_link_key B1:96:11:68:9C:09 type 0x04 pin_len 0 store_hint 1 [CHG] Device B1:96:11:68:9C:09 Bonded: yes [DEL] Device 6A:98:7A:08:0F:B8 6A-98-7A-08-0F-B8 [CHG] Device B1:96:11:68:9C:09 ServicesResolved: yes [CHG] Device B1:96:11:68:9C:09 Paired: yes Pairing successful5X II代]# [DEL] Device 6C:59:25:E5:66:77 6C-59-25-E5-66-77 [DEL] Device 61:CC:7D:CE:20:4E 61-CC-7D-CE-20-4E [DEL] Device 64:C1:4B:76:C1:80 64-C1-4B-76-C1-80 [DEL] Device 72:50:16:14:52:A6 72-50-16-14-52-A6 hci0 B1:96:11:68:9C:09 type BR/EDR disconnected with reason 2 [CHG] Device B1:96:11:68:9C:09 ServicesResolved: no [CHG] Device B1:96:11:68:9C:09 Connected: no [bluetooth]#trust B1:96:11:68:9C:09 [CHG] Device B1:96:11:68:9C:09 Trusted: yes Changing B1:96:11:68:9C:09 trust succeeded [bluetooth]#connect B1:96:11:68:9C:09 Attempting to connect to B1:96:11:68:9C:09 hci0 B1:96:11:68:9C:09 type BR/EDR connected eir_len 34 [CHG] Device B1:96:11:68:9C:09 Connected: yes [NEW] Endpoint /org/bluez/hci0/dev_B1_96_11_68_9C_09/sep1 [NEW] Endpoint /org/bluez/hci0/dev_B1_96_11_68_9C_09/sep2 [NEW] Transport /org/bluez/hci0/dev_B1_96_11_68_9C_09/sep1/fd0 [CHG] Transport /org/bluez/hci0/dev_B1_96_11_68_9C_09/sep1/fd0 Delay: 0x05dc (1500) Connection successfulII代]# [CHG] Device B1:96:11:68:9C:09 ServicesResolved: yes [联想thinkplus-HE05X II代]#quit • Step 4: Start pipewire and wireplumber Service then list and choose default Audio Source/Sink Card root@imx8mpevk:~#systemctl --user start pipewire wireplumber root@imx8mpevk:~#wpctl status PipeWire 'pipewire-0' [1.0.5, root@imx8mpevk, cookie:831282980] Clients: 32. WirePlumber [1.0.5, root@imx8mpevk, pid:1528] 40. WirePlumber [export] [1.0.5, root@imx8mpevk, pid:1528] 87. wpctl [1.0.5, root@imx8mpevk, pid:1552] Audio -Devices： 41. Built-in Audio [alsa] 42. Built-in Audio [alsa] 43. Built-in Audio [alsa] 44. Built-in Audio [alsa] 45. Built-in Audio [alsa] 81. 联想thinkplus-HE05X II代 [bluez5] -Sinks： 47. Built-in Audio Mono [vol: 0.40] 48. Built-in Audio Stereo [vol: 0.40] 50. Built-in Audio Stereo [vol: 0.40] 58. Built-in Audio Digital Stereo (IEC958) [vol: 0.40] * 82. 联想thinkplus-HE05X II代 [vol: 0.40] -Sources: 46. Built-in Audio Mono [vol: 1.00] 49. Built-in Audio Stereo [vol: 1.00] 51. Built-in Audio Stereo [vol: 1.00] * 59. Built-in Audio Digital Stereo (IEC958) [vol: 1.00] -Filters: -Streams: Video -Devices: 52. mxc-isi-m2m_v1 [v4l2] 53. vsi_v4l2enc [v4l2] 54. vsi_v4l2dec [v4l2] Streams: Settings Default Configured Devices: root@imx8mpevk:~#wpctl set-default 82 root@imx8mpevk:~#wpctl set-default 59 root@imx8mpevk:~# wpctl status PipeWire 'pipewire-0' [1.0.5, root@imx8mpevk, cookie:831282980] Clients: 32. WirePlumber [1.0.5, root@imx8mpevk, pid:1528] 40. WirePlumber [export] [1.0.5, root@imx8mpevk, pid:1528] 87. wpctl [1.0.5, root@imx8mpevk, pid:1572] Audio 41. Built-in Audio [alsa] 42. Built-in Audio [alsa] 43. Built-in Audio [alsa] 44. Built-in Audio [alsa] 45. Built-in Audio [alsa] 81. 联想thinkplus-HE05X II代 [bluez5] 47. Built-in Audio Mono [vol: 0.40] 48. Built-in Audio Stereo [vol: 0.40] 50. Built-in Audio Stereo [vol: 0.40] 58. Built-in Audio Digital Stereo (IEC958) [vol: 0.40] * 82. 联想thinkplus-HE05X II代 [vol: 0.40] 46. Built-in Audio Mono [vol: 1.00] 49. Built-in Audio Stereo [vol: 1.00] 51. Built-in Audio Stereo [vol: 1.00] * 59. Built-in Audio Digital Stereo (IEC958) [vol: 1.00] 分区Bluetooth 的第4 页 * 59. Built-in Audio Digital Stereo (IEC958) [vol: 1.00] Streams: Video 52. mxc-isi-m2m_v1 [v4l2] 53. vsi_v4l2enc [v4l2] 54. vsi_v4l2dec [v4l2] Streams: Settings Default Configured Devices: 0. Audio/Sink bluez_output.B1_96_11_68_9C_09.1 1. Audio/Source alsa_input.platform-sound-xcvr.iec958-stereo Step 5: Copy、Play and Enjoy Music Drag the music file yesterday-once-more.wavto I.MX8MP-EVK board by connecting Windows PC and I.MX8MP-EVK board into one local area network. root@imx8mpevk:~# pw-play -v ./yesterday-once-more.wav sndfile: opened file "yesterday-once-more.wav" format 00010002 channels:2 rate:44100 sndfile: using default channel map: FL,FR PCM: fmt:s16 rate:44100 channels:2 width:2 rate:44100 latency:4410 (0.100s) connecting playback stream; target=(null) stream state changed unconnected -> connecting stream param change: Spa:Enum:ParamId:Latency stream param change: Spa:Enum:ParamId:Tag stream param change: Spa:Enum:ParamId:Props stream properties: application.name = "pw-play" node.name = "pw-play" media.software = "Lavf58.29.100" media.format = "WAV (Microsoft)" node.rate = "1/44100" node.latency = "4410/44100" media.type = "Audio" media.category = "Playback" media.role media.filename = "yesterday-once-more.wav" media.name = "yesterday-once-more.wav" stream.is-live = "true" node.want-driver = "true" node.autoconnect = "true" media.class = "Stream/Output/Audio" remote 0 is named "pipewire-0" stream state changed connecting -> paused stream param change: Spa:Enum:ParamId:Props stream param change: Spa:Enum:ParamId:Latency stream param change: Spa:Enum:ParamId:Latency stream param change: Spa:Enum:ParamId:Format stream state changed paused -> streaming stream set volume to 1.000 -success stream node 88 stream time: now:0 rate:1/48000 ticks:0 delay:9248 queued:0 buffered:0 buffers:0 avail:2 size:0 stream time: now:4821374572568 rate:1/48000 ticks:49152 delay:9248 queued:1882 buffered:32 buffers:1 avail:1 size:1882 stream time: now:4822355905886 rate:1/48000 ticks:96256 delay:9248 queued:1882 buffered:32 buffers:1 avail:1 size:1882 stream time: now:4823379905870 rate:1/48000 ticks:145408 delay:9248 queued:1881 buffered:32 buffers:1 avail:1 size:1881 Finished By Christine.Li Jul 22th,2026.