Executing from LPDDR2

[chrispage]

I am currently using a Micron LPDDR2 (MT42L32M16D1) part.  I have it configured and have been able to run a memory test executing from internal SRAM that can write and read from the LPDDR2 memory without any errors.  When I go to execute out of the LPDDR2, I am receiving errors(chip is going off into the weeds) upon execution of any instruction that utilizes the stack(push, bl, etc.).  If I adjust the TBST_INT_INTERVAL from 2 to 4, I am able to use a debugger and step through these instructions without error, but if I attempt to run without stepping, I see the crash again.  Adjusting the interval more in either direction does not help (if anything makes it worse). Any idea which DRAM configurations/settings would be causing this problem?  Thanks.

[juangutierrez]

I just sent you a direct message about some code I found, I don't know if that helps, but seems to have some code related to LPDDR2.

I have neither tried nor tested. Just sharing in case.

[naoumgitnik]

Just a comment - this code is posted on the Freescale-internal Vybrid_FAE support forum in the thread discussing LPDDR2 settings.

/Naoum.

[naoumgitnik]

Hello Everybody,

Attached are:

1. Excerpt from our LPDDR2 Validation board schematic,
2. DDR controller tuning document (just in case).

Unfortunately, based on what I learned from the SW Apps people, I am afraid this is all we can can help with, as of now; and the reason is that, based on our market observations, Vybrid customers are using DDR3 way more frequently that LPDDR2, so, with our limited resources, the department's focus is on the former - boards, code examples, etc. For the latter, though, we have only run validation tests, but not really beyond that point.

Sincerely yours, Naoum Gitnik.

[juangutierrez]

alejandrolozano would you have the dma.h file for the lpddr2 project you posted on https://community.freescale.com/message/364994#364994 that you can share, please?

[naoumgitnik]

Chris,

Attached are settings for our validation board - may you use them, please?

Regards, Naoum Gitnik.

[chrispage]

I have not tried 200MHz yet, but I am in the process of giving it a try right now to see if the same problems exist.  Was executing out of the LPDDR2 tested with the 200MHz code sample that was provided?  Also, are there any other register changes needed for the example code to run (for example clock register settings).