About setting PHY Register 03 and PHY Register 04

cancel
Showing results for 
Search instead for 
Did you mean: 

About setting PHY Register 03 and PHY Register 04

Jump to solution
528 Views
keisukewatanabe
Contributor III

Dear support,

34.5.166 PHY Register 03 (DDRMC_PHY03)

34.5.167 PHY Register 04 (DDRMC_PHY04)

When I use DLL at Auto-configure mode, it is necessary to set this register?

Best regards,

Keisuke Watanabe

Labels (1)
1 Solution
145 Views
juangutierrez
NXP Employee
NXP Employee

Yes, that is correct but ENCODER is not the DLL_LOCK_VALUE

It is related to but not the same. Basically you don't need to worry about this ENCODER number. It is internal data and It should be transparent for you in auto-configure mode.

At the end you only need to tell what is the percentage of one-cycle delay you want.

So if you want 50% then DLL_WRITE_DL = 64  ===>  DLL_WRITE_DL/128 = 0.5

                      25% then  DLL_WRITE_DL = 32 ===> DLL_WRITE_DL/128 = 0.25

View solution in original post

0 Kudos
12 Replies
145 Views
ioseph_martinez
NXP Employee
NXP Employee

Keisuke,

The DLL corresponds to an internal module which is delay locked loop.

In the case of phy_03 this just represents the starting value for the DLL, the DLL eventually will find a value to lock. In general, this will be transparent for the user so just set this register to 0x4 as recommened.

In the case of phy_04 I am currently investigating, I let you know when I have more details.

Regards,

Ioseph

145 Views
karina_valencia
NXP Apps Support
NXP Apps Support

ioseph_martinez do you have an update on this case?

0 Kudos
145 Views
YumotoTaku
NXP Employee
NXP Employee

Hello, Ioseph-san,

Is it ok to set PHY_03 as 0x04 with Auto configure mode?

Could you also confirm PHY_04 iwth Auto conifugure mode?

Best Regards

Taku

0 Kudos
145 Views
karina_valencia
NXP Apps Support
NXP Apps Support

juangutierrez can you continue with the follow up on this case?

0 Kudos
145 Views
juangutierrez
NXP Employee
NXP Employee

For Auto configure mode DDRMC_PHY03[DLL_START_POINT] you can set it to 0x04.

This value will be the starting point for the phase detector which will lock at a certain value called DLL_LOCK_VALUE which indicates the delay of one cycle.

The number of delay elements that are needed to capture an entire clock cycle is then converted into an unsigned integer named encoder [7:0]

Let say the period of 1 cycle is 100ms and encoder = 100.

Hence each delay element delays the signal 1ms and encoder = 100  which means that 100 delay elements are needed to delay the signal one complete cycle (100ms)

The actual delay setting for the delay lines is calculated by multiplying the encoder [7:0] integer by the parameter settings for each delay line and then dividing by 128 and rounding.

So if you want to delay the signal 25 ms, you need to set DDRMC_PHY04[DLL_WRITE_D] = 0x20 = 32

Numer of delay elemets DLL_WRITE_DL/128 * ENCODER =    32/128 * 100 = 25

This means internally 25 delay elements (of 1ms) will be used to delay the signal 25ms

In conclusion you still need to set DDRMC_PHY04[DLL_WRITE_D] to express the percentage (DLL_WRITE_D/128)  you want to delay the output signal

145 Views
YumotoTaku
NXP Employee
NXP Employee

Hello, Juan-san,

Thank you for reply.


In auto configure mode, user set as following;

PHY03(DLL_START_POINT) should be set 0x04.

target delay is calculated as below;

PHY04_DLL_WRITE_DL/128 * ENCODER. (ENCODER is DLL_LOCK_VALUE)

Is it correct? Sorry, I could not understand which register is ENCODER...

Best Regards
Taku.

0 Kudos
146 Views
juangutierrez
NXP Employee
NXP Employee

Yes, that is correct but ENCODER is not the DLL_LOCK_VALUE

It is related to but not the same. Basically you don't need to worry about this ENCODER number. It is internal data and It should be transparent for you in auto-configure mode.

At the end you only need to tell what is the percentage of one-cycle delay you want.

So if you want 50% then DLL_WRITE_DL = 64  ===>  DLL_WRITE_DL/128 = 0.5

                      25% then  DLL_WRITE_DL = 32 ===> DLL_WRITE_DL/128 = 0.25

View solution in original post

0 Kudos
145 Views
YumotoTaku
NXP Employee
NXP Employee

Hello, Juan-san,

Thank you. I understand it.

PHY04 can configure the how delay the data write from clock. if clock period is 10ns and would like to make 2.5ns delay (25%delay). user should set this register as 0x20.

ddrmc_phy04.png

If my understanding is not correct, could you correct it?

Best Regards

Taku.

145 Views
juangutierrez
NXP Employee
NXP Employee

Yes, that's correct

0 Kudos
145 Views
YumotoTaku
NXP Employee
NXP Employee

Jua-san,

Thank you!

Best Regards

Taku

0 Kudos
145 Views
timesyssupport
Senior Contributor II

Hello Keisuke,

At this time, the engineer most familiar with Vybrid is travelling for training internationally. When he is next available, I will ask him to review this inquiry and provide feedback.

Regards,

Timesys Support

145 Views
karina_valencia
NXP Apps Support
NXP Apps Support

timesyssupport can you help on this case?

0 Kudos