IFC Flash Timing Register

[faizmajeed]

Hi!

I am using T1042 and interfacing NOR Flash (part no : MT28EW01GABA1LPC-1SIT ) to IFC.

I have done most of its setting but now i am confused in Flash Timing Registers. I have read the reference manual but i cannot decide that what values should i set in all timing registers and what is frequency of ip_clk that is used in diagrams of reference manual.

Thank you

[r8070z · Accepted solution]

Have a great day,

The ip_clk is the IFC module input clock. Frequency of the ip_clk is 1/2 platform Clock – refer to the QorIQ T1040 Reference Manual, 4.6.7.2 IP Logic Clock Distribution and Configuration.

How fields of the timing registers define NOR read/write timing you can see on Figure 24-38. Read cycle timing and Figure 24-40. Write cycle timing in the manual. F.e. let platform clock is 500 MHz (i.e. ip_clk cycle tIP = 2/500MHz = 4 ns). According to the datasheets the MT28EW01GABA1LPC has (OE# LOW to output valid) tOE=25 ns; the T1042 IFC input has 2* tIP setup time. So from Figure 24-38 we can conclude that TRAD*tIP should cover tOE+tSetup i.e. TRAD should be >= (floor(25ns/4)+1) +2 = (6+1)+2 = 9.

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[faizmajeed]

I got your point, But i have read in T1042 Manual that we can set IFC max clock 100MHZ . How can i set it 500MHZ

[r8070z]

I wrote let “platform clock is 500 MHz” and “The ip_clk is the IFC module input clock”. It is not output clock on the IFC_CLK pin which they name as IFC clock frequency.