IFC chip select algorithm

[faizmajeed]

What is relation between 24bit base address in IFC registers and 24bit base address in Local Access window registers.
These are two addresses that are compared during chip select algorithm as discussed in Address Masking Register?
do i have to create different Local access window for each chip select of IFC?

I am not getting the idea that how processor will enable chip select by using IFC registers base address and Local Access window registers. I think reference manual contain limited information about address translation.

Also suggest me some documents which help me to understand whole memory mapping process used by T1042 specially for IFC.

Processor i am using : T1042

[ufedor]

In general Local Access windows are used to bind memory-mapped target controllers with specific areas in the SOC address space - read QorIQ T1040 Reference Manual, 2.3 Local Access Windows (LAWs).

Note that the e5500 MMU uses 36-bit physical addresses, but IFC is capable to decode only 32-bit addresses - this is one of the reasons why the LAWs are needed.

The T1042 LAW is capable to determine a window anywhere in the 36-bit internal address space - see the RM, 2.4.1 LAWn base address register high (LAW_LAWBARHn) and 2.4.2 LAWn base address register low (LAW_LAWBARLn).

Target controller of the LAW is specified in the LAW_LAWARn[TRGT_ID].

In case of the IFC the addressing sequence is as follows:

1) Core MMU (or another SOC master) generates a transaction with 36-bit target address

2) If the address is within the IFC LAW the transaction is dispatched to the IFC

3) The IFC uses lower 32 bits of the address to determine specific bank - refer to the RM, 24.3.4 Address Mask register (IFC_AMASKn).

[faizmajeed]

Now I understood that 

core MMU generates a transaction with 36-bit target address. it is compared with LAW

MMU_address [0:23] == LAW_LAWBARHn[28:31] + LAWBARLn[0:19] 

if it is true for IFC then

MMU_address[35:28] ,(AMn[0:15]&MMU_address[27:12]) == BASE_ADDRn[0:7], (BASE_ADDRn[8:23] & AMn[0:15])

This mean that we should set the base address of IFC_CSPRn and IFC_CSPRn_EXT so that it should be equal to base address of LAW that is specific for IFC ?

if it is true then what would be address that will go on IFC output address pins?

[ufedor]

Please create a Technical Case to discuss the issue further:

https://community.freescale.com/thread/381898