DDR3 Power Connection on T1024RDB

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DDR3 Power Connection on T1024RDB

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bltuna
Contributor II

Hi,

Below is the power connection of the DDR3 that is presented on the T1024RDB schematic. I couldn't understand why such a connection (highlighted portion) is made.

ddr3.PNG

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r8070z
NXP Employee
NXP Employee

pastedImage_1.png

This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”

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r8070z
NXP Employee
NXP Employee

pastedImage_1.png

This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”