Hi,
Below is the power connection of the DDR3 that is presented on the T1024RDB schematic. I couldn't understand why such a connection (highlighted portion) is made.
This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”
This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”
