The following is an assumption requirement from safety manual 6.0 for 32k388. for e), the application shall trigger timer or is there any dedicated timer for AES eviction?     ... View more

I'm searching for the functional safety certification for the following drivers: Real-Time-Drivers (RTD) 3.0.0 RTM ASIL D Safety Peripheral Driver (SPD) 1.0.3 RTM ASIL D System basic chip FS26 (Sbc_fs26) 2.0.1 FBR ASIL D In the FlexNetOperations I can find the release quality and the integrity level in the Safety Manual or the release notes, but no explicit certification document is given. Where can I find these functional safety certification for specific drivers?  ... View more

One customer wants to know what the differences between QM(SafetyDoc) and ASIL-B are. I think that QM(SafetyDoc) just follows quality document to support ISO26262 Functional safety compared to ASIL-B standard. So, QM(SafetyDoc) does not satisfy ISO26262 functional safety requirements including FMEA analysis. ... View more

Hi NXP Team, As suggested in safety manual of the microcontroller I have enabled the following, 1. PLL fed by SOSC and the core clock mux is selected as output from PLL. 2. Enabled loss of clock monitor for SOSC and enabled the interrupt. 3. Enabled loss of lock monitor for SPLL and enabled the interrupt.   Now, In the interrupt I am trying to switch the core clock to FIRC before safe shutdown. But, whenever I perform the clock switch the system hangs in a loop withinin FREERTOS  kernel.  Clock Configurations are, OSC frequency: 8Mhz PLL output frequency: 96Mhz Core clock divider: Divide by 2 Core clock frequency: 48Mhz Below is the code snippet of interrupt service routine, void scg_isr () {     /* Check if the system oscillator clock error detected */     if ((IP_SCG->SOSCCSR & SCG_SOSCCSR_SOSCCM_MASK) ==     SCG_SOSCCSR_SOSCCM_MASK)     {         /* Unlock the control status register */         CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SOSCCSR_LK_SHIFT);         /* Disable SOSC monitor as the core clock is switched to FIRC */         CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SOSCCSR_SOSCCM_SHIFT);         CLEAR_BIT (IP_SCG->SOSCCSR,         SCG_SOSCCSR_SOSCCMRE_SHIFT); }         /* Check if the PLL lock error detected */         if ((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLCM_MASK) == SCG_SPLLCSR_SPLLCM_MASK)         {                 /* Unlock the control status register */                 FUSA_CLEAR_BIT (IP_SCG->SPLLCSR, SCG_SPLLCSR_LK_SHIFT);                /* Disable SOSC monitor as the core clock is switched to FIRC */                FUSA_CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SPLLCSR_SPLLCM_SHIFT);                FUSA_CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SPLLCSR_SPLLCM_SHIFT); }            /** Change core clock divider to divide by 1**/         MODIFY_REG(IP_SCG->RCCR,SCG_RCCR_DIVCORE_MASK, SCG_RCCR_DIVCORE(0U));         while ((IP_SCG->CSR & SCG_CSR_DIVCORE_MASK) != SCG_CSR_DIVCORE(0U))         {              // Do nothing          }         /** Switch core clock source to FIRC */         MODIFY_REG(IP_SCG->RCCR,SCG_RCCR_SCS_MASK, SCG_RCCR_SCS(3U));         while ((IP_SCG->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(3U))         {          // Do nothing         }   } Kindly help me out with this. Regards, Ajeeth Kumar ... View more