Hello, I have questions regarding some of the safety mechanisms that require NXP's clarification.  1. The Safety Manual Rev 2. SM17 (table 11) states both "Medium" and "60% diagnostic coverage, which cannot both be true. Based on the fact that LFM requires ASIL B (with a DC of 60% or greater), it is assumed this is a typographical error. Please confirm the diagnostic coverage for SM17. 2. While DC of 60% is acceptable per ISO 26262, Part4-6.4.2.5, is there a reason that both ABIST and LBIST cannot meet 90%? Please advise. 3. VDDIOMON, VCOREMON, VMONx, and HVLDO monitors all have safety mechanisms for OV, UV, and OV&UV detection. Where the latter is SMxC. For example, I don't understand why there is a separate mechanism for VMON1 OV (SM3A) and UV (SM3B), and a different mechanism for the combination (SM3C). Further, there is a further set of mechanism to encompass all monitors OV, UV, and OV&UV (SM18, SM19, SM20). I've reviewed the FMEDA and it still isn't clear to me what the difference truly is and how to use each. Please advise as they all reference the same respective safety manual sections. I look forward to reviewing your feedback. Thanks, Jeff     ... View more

Where can I find documentation that the S32K1 and S32K3 RTDs are compliant with ASPICE? Is there a certificate available?   ... View more

I want S32k3 assessment report. S32k3 SAF 1.0.3 version SCST 1.0.5 version Like safety SW assessment summary document ... View more

Software assumption Application software activates pull-down on RESET_b pad before running the safety application. Question#1) To activate the pull-down on RESET_b, the following shall be done?   Identify the MSCR Register for RESET_B: RESET_B is typically mapped to PTA5, which corresponds to SIUL2_MSCR5. Set the Pull Enable and Pull Select Bits: PUE (bit 13) = 1 → Enables internal pull resistor. PUS (bit 11) = 0 → Selects pull-down (when PUE is enabled). Optional: Enable Input Buffer (if needed for monitoring): IBE (bit 19) = 1 Optional: Disable Output Buffer (if not used): OBE (bit 21) = 0   Rationale Ensures that the chip enters a chip safe state if the RESET_b pin gets disconnected. Recommendation — Question#2) In order to detect the Reset_b pin is disconnected,  one of the following shall be done?   Option 1: Use MC_RGM.FES[F_EXR] Monitor this flag to see if RESET_B was unexpectedly asserted. If it is never set, and you expect external resets, it may indicate a disconnection. Option 2: Use a GPIO for Redundancy If possible, connect RESET_B to a GPIO input on the MCU or another monitoring device. Periodically sample the pin level to verify it is high during normal operation. This allows software to detect if the pin is floating or stuck low. Option 3: External Watchdog or SBC Monitoring Many systems use an external Safety Power Management IC (PMIC) or SBC that monitors RESET_B. These devices can detect if RESET_B is not behaving as expected and report faults. ... View more

  [Q1]The following is the detail information and regarding the fault reporting, the following show RGM and also the 2nd capture from the attachment shows NCF4.  In this case it reports to RGM however also NCF4 is triggered as well?   2nd capture   [Q2]Also for the following case, in case the bit MCRS[PEG] is triggered, then NCF [x] can be also triggered as well?   [Q3]Also for the following case, in case the bit [MISR] is set, then also corresponding NCF[x] can be also set(triggered)? [Q4]In the following case, the CRC error can set corresponding NCF[x] as well?        ... View more