Hi NXP Team,
As suggested in safety manual of the microcontroller I have enabled the following,
1. PLL fed by SOSC and the core clock mux is selected as output from PLL.
2. Enabled loss of clock monitor for SOSC and enabled the interrupt.
3. Enabled loss of lock monitor for SPLL and enabled the interrupt.
Now, In the interrupt I am trying to switch the core clock to FIRC before safe shutdown. But, whenever I perform the clock switch the system hangs in a loop withinin FREERTOS kernel.
Clock Configurations are,
OSC frequency: 8Mhz
PLL output frequency: 96Mhz
Core clock divider: Divide by 2
Core clock frequency: 48Mhz
Below is the code snippet of interrupt service routine,
void scg_isr ()
{
/* Check if the system oscillator clock error detected */
if ((IP_SCG->SOSCCSR & SCG_SOSCCSR_SOSCCM_MASK) == SCG_SOSCCSR_SOSCCM_MASK)
{
/* Unlock the control status register */
CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SOSCCSR_LK_SHIFT);
/* Disable SOSC monitor as the core clock is switched to FIRC */
CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SOSCCSR_SOSCCM_SHIFT);
CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SOSCCSR_SOSCCMRE_SHIFT);
}
/* Check if the PLL lock error detected */
if ((IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLCM_MASK) == SCG_SPLLCSR_SPLLCM_MASK)
{
/* Unlock the control status register */
FUSA_CLEAR_BIT (IP_SCG->SPLLCSR, SCG_SPLLCSR_LK_SHIFT);
/* Disable SOSC monitor as the core clock is switched to FIRC */
FUSA_CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SPLLCSR_SPLLCM_SHIFT);
FUSA_CLEAR_BIT (IP_SCG->SOSCCSR, SCG_SPLLCSR_SPLLCM_SHIFT);
}
/** Change core clock divider to divide by 1**/
MODIFY_REG(IP_SCG->RCCR,SCG_RCCR_DIVCORE_MASK, SCG_RCCR_DIVCORE(0U));
while ((IP_SCG->CSR & SCG_CSR_DIVCORE_MASK) != SCG_CSR_DIVCORE(0U))
{
// Do nothing
}
/** Switch core clock source to FIRC */
MODIFY_REG(IP_SCG->RCCR,SCG_RCCR_SCS_MASK, SCG_RCCR_SCS(3U));
while ((IP_SCG->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(3U))
{
// Do nothing
}
}
Kindly help me out with this.
Regards,
Ajeeth Kumar
RadoslavB
Hi Ajeeth,
please try to repost the topic in the S32K community as this is HW specific issue.
S32K - NXP Community
Please try to consider using RTD drivers (Mcu module) for the clock switch operation.
The low level registers control in the Safety Manual Implementation hint is just an example, using RTD drivers is allowed as RTD is ISO26262 compliant.
Kind Regards,
Radoslav
antoinedubois
Hi Ajeeth,
we are looking into the issue and will get back to you soon.
RadoslavB
antoinedubois