select clock for modules with PCC?

[JeorgeB]

Hi, 

I wanna to use LPSPI. assume there is a SOSC and Core CLK is 80MHz. bus clock is 40MHz. FIRC is 48MHz.

Can I use FIRC as input clock for LPSPI module ? (it is bigger than BUS CLK)

in page 566 for LPSPI, RM says : "Maximum frequency governed by BUS_CLK"

Thanks.

[Robin_Shen]

Hi JeorgeB,

You can not use FIRC(48MHz) as input clock for LPSPI module as it is bigger than BUS_CLK(40MHz).

Maximum frequency governed by BUS_CLK.pngTable 27-9. Peripheral module clocking.png

Best Regards,
Robin
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[JeorgeB]

Hi Robin, A. what is BUS_CLK role in here? is it only for communication between Master and the module? B. If we gated off this clock [CGC], the module will be switched off (do not consume power)? or we should disable [PCS] clock? C. Assume we, use prescaler and SCK divider with register appropriate setting, and LPSPI SCK clock is 8MHz, is there same limitation by using FIRC-48MHZ? Thanks.

[Robin_Shen · Accepted solution]

AFigure 51-1. Block Diagram.png

BFigure 10. LPSPI Example Block Diagram.png

CGC low power.png

C. The limitation is for Functional clock, not the clock after divider. Same limitation by using FIRC-48MHz (>40MHz BUS_CLK)