Hi,
I wanna to use LPSPI. assume there is a SOSC and Core CLK is 80MHz. bus clock is 40MHz. FIRC is 48MHz.
Can I use FIRC as input clock for LPSPI module ? (it is bigger than BUS CLK)
in page 566 for LPSPI, RM says : "Maximum frequency governed by BUS_CLK"
Thanks.
Solved! Go to Solution.
A
B
C. The limitation is for Functional clock, not the clock after divider. Same limitation by using FIRC-48MHz (>40MHz BUS_CLK)
Hi JeorgeB,
You can not use FIRC(48MHz) as input clock for LPSPI module as it is bigger than BUS_CLK(40MHz).
Best Regards,
Robin
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A
B
C. The limitation is for Functional clock, not the clock after divider. Same limitation by using FIRC-48MHz (>40MHz BUS_CLK)