how to sppedup HSE initialization use IVT config

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how to sppedup HSE initialization use IVT config

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PINKMAN
Contributor III

hi expert:

i found that the HSE initialize time ia too long(50ms),i want to know how to   spped up HSE use  IVT config enable PLL.my chip is S32K312,Crystal oscillator iS 20MHZ, PLL PHI0 is 120MZ

PINKMAN_0-1751951742888.png

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

It seems that you did not download the Example code corresponding to AN744511-Secure Boot Application note v0.1.1.0(1.1).pdf:

sw745310 SecureBootAppNoteDemo PDF Rev 1.0 Apr 4, 2022 28.61 MB

sw745310 SecureBootAppNoteDemo\SourceCode\src\main.c

/* enable utest fxosc usage and dcf clock option
* with pll enable in ivt.beq, secure boot verification can be accelerated */
EnableFXOSCUsage();

ChangeDcfClockOption();

The latest s32k3_hse_lib_rtd400hf01_20250627.7z also includes this function. Considering that you are a Chinese customer, it is recommended to contact FAE to obtain it.

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

Have you referred to the methods described in chapter 9.3. Improve performance of Secure Boot Application note v0.1.1.0?

Best Regards,
Robin
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PINKMAN
Contributor III

hello:

i know the sequence is that config clock frequency and  HSE clock option in UTEST,AND then the BCW bit PLL_ENABLE AND BOOT SEQ will make sense.

in the startup_cm7.s ,I open the PLL_ENABLE AND BOOT SEQ as below

.long (CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT) | (CM7_2_ENABLE << CM7_2_ENABLE_SHIFT) | (CM7_3_ENABLE << CM7_3_ENABLE_SHIFT) | (PLL_ENABLE << PLL_ENABLE_SHIFT) | (BOOT_SEQ_ENABLE << BOOT_SEQ_ENABLE_SHIFT)

PINKMAN_0-1751963826089.png

but i don't know how to write UTEST?

 

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

It seems that you did not download the Example code corresponding to AN744511-Secure Boot Application note v0.1.1.0(1.1).pdf:

sw745310 SecureBootAppNoteDemo PDF Rev 1.0 Apr 4, 2022 28.61 MB

sw745310 SecureBootAppNoteDemo\SourceCode\src\main.c

/* enable utest fxosc usage and dcf clock option
* with pll enable in ivt.beq, secure boot verification can be accelerated */
EnableFXOSCUsage();

ChangeDcfClockOption();

The latest s32k3_hse_lib_rtd400hf01_20250627.7z also includes this function. Considering that you are a Chinese customer, it is recommended to contact FAE to obtain it.

 

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PINKMAN
Contributor III
i change the IVT config as below,
(CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT) | (CM7_2_ENABLE << CM7_2_ENABLE_SHIFT) | (CM7_3_ENABLE << CM7_3_ENABLE_SHIFT) | (PLL_ENABLE << PLL_ENABLE_SHIFT)
but it didn't work
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